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194 条记录 (耗时 0.033 秒)

    Semiconductor IC device having sense amplifier circuit
    32.
    发明授权
    Semiconductor IC device having sense amplifier circuit 失效
    具有读出放大器电路的半导体IC器件

    公开(公告)号：US5300839A

    公开(公告)日：1994-04-05

    申请号：US865852

    申请日：1992-04-09

    申请人： Takayuki Kawahara ,  Takesada Akiba ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Kiyoo Itoh ,  Takeshi Sakata

    发明人： Takayuki Kawahara ,  Takesada Akiba ,  Goro Kitsukawa ,  Yoshiki Kawajiri ,  Kiyoo Itoh ,  Takeshi Sakata

    IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C11/401 ,  G11C11/4091 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： G11C7/065 ,  G11C11/4091 ,  G11C7/062

    摘要： A sense amplifier circuit is provided for sensing a very small signal includes two MOS transistors responsive to a differential voltage between first and second input signal lines to conduct a differential operation and switches respectively connected between drain regions and gate regions respectively of the two MOS transistors. Before the circuit senses and amplifies the signal, the switches are turned on to generate threshold voltages between the gate regions and the source regions respectively of the two transistors. Consequently, according to the variation in the threshold voltage between the respective transistors, a self-adjustment is achieved on bias voltages of the transistors before the signal amplification. The sense amplifier circuit resultantly develops its operation independent of the variation in the threshold voltage. One use for this sense amplifier circuit is to serve as a sense amplifier for a DRAM.

    摘要翻译： 提供了一种用于感测非常小的信号的读出放大器电路，其包括响应于第一和第二输入信号线之间的差分电压的两个MOS晶体管，以分别连接在两个MOS晶体管的漏极区域和栅极区域之间的差分操作和开关。 在电路感测并放大信号之前，开关导通，以在两个晶体管的栅极区域和源极区域之间产生阈值电压。 因此，根据各个晶体管之间的阈值电压的变化，在信号放大之前对晶体管的偏压进行自调整。 读出放大器电路结果是独立于阈值电压的变化而发展其工作。 该感测放大器电路的一个用途是用作DRAM的读出放大器。

    Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier
    35.
    发明授权
    Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier 失效
    具有低功耗的半导体电路具有发射极耦合逻辑或差分放大器

    公开(公告)号：US4999519A

    公开(公告)日：1991-03-12

    申请号：US277992

    申请日：1988-11-30

    申请人： Goro Kitsukawa ,  Kazumasa Yanagisawa ,  Takayuki Kawahara ,  Ryoichi Hori ,  Yoshinobu Nakagome ,  Noriyuki Hamma ,  Kiyoo Itoh ,  Hiromi Tukada

    发明人： Goro Kitsukawa ,  Kazumasa Yanagisawa ,  Takayuki Kawahara ,  Ryoichi Hori ,  Yoshinobu Nakagome ,  Noriyuki Hamma ,  Kiyoo Itoh ,  Hiromi Tukada

    IPC分类号： H03K19/00

    CPC分类号： H03K19/0016

    摘要： An ECL circuit wherein a current switch and an emitter follower are coupled, is so constructed that, in a standby mode, the current switch has its current cut off or rendered smaller than in an operating mode. In addition, the ECL circuit comprises means for decoupling a load resistance of the current switch and a base of the emitter follower in the case of cutting off the current of the current switch, or means for increasing the load resistance of the current switch in the case of rendering the current of the current switch smaller. The semiconductor circuit of the present invention can reduce the power consumption of the ECL circuit and can suppress fluctuations in the voltage levels of the outputs of the ECL circuit.

    摘要翻译： 其中电流开关和射极跟随器耦合的ECL电路被构造成使得在待机模式中，电流开关的电流切断或变得比操作模式小。 此外，ECL电路包括在切断电流开关的电流的情况下解耦电流开关的负载电阻和射极跟随器的基极的装置，或用于增加电流开关的负载电阻的装置 使当前开关的电流变小的情况。 本发明的半导体电路可以降低ECL电路的功耗，并且可以抑制ECL电路的输出的电压电平的波动。

    Semiconductor storage device
    37.
    发明授权
    Semiconductor storage device 失效
    半导体存储设备

    公开(公告)号：US08427864B2

    公开(公告)日：2013-04-23

    申请号：US13375751

    申请日：2010-06-02

    申请人： Takayuki Kawahara ,  Kiyoo Itoh ,  Riichiro Takemura ,  Kenchi Ito

    发明人： Takayuki Kawahara ,  Kiyoo Itoh ,  Riichiro Takemura ,  Kenchi Ito

    IPC分类号： G11C11/00

    CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

    摘要： To write information on a memory cell of SPRAM formed of an MOS transistor and a tunnel magnetoresistive element, the memory cell is supplied with a current in a direction opposite to a direction of a current required for writing the information on the memory cell, and then, the memory cell is supplied with a current required for writing. In this manner, even when the same information is sequentially written on the memory cell, since the currents in the two directions are caused to flow in pairs in the tunnel magnetoresistive element of the memory cell each time information is rewritten, deterioration of a film that forms the tunnel magnetoresistive element can be suppressed. Therefore, reliability of the SPRAM can be improved.

    摘要翻译： 为了在由MOS晶体管和隧道磁阻元件形成的SPRAM的存储单元上写入信息，向存储单元提供与在存储单元上写入信息所需的电流方向相反的方向的电流，然后 ，为存储单元提供写入所需的电流。 以这种方式，即使当相同的信息被顺序地写入存储单元时，由于每当信息被重写时，两个方向上的电流成对地在存储单元的隧道磁阻元件中成对流动，所以， 可以抑制隧道磁阻元件的形成。 因此，可以提高SPRAM的可靠性。

    SEMICONDUCTOR RECORDING DEVICE
    38.
    发明申请
    SEMICONDUCTOR RECORDING DEVICE 失效
    半导体记录装置

    公开(公告)号：US20130051134A1

    公开(公告)日：2013-02-28

    申请号：US13643880

    申请日：2011-04-05

    申请人： Takayuki Kawahara ,  Riichiro Takemura ,  Takashi Ishigaki ,  Kiyoo Itoh

    发明人： Takayuki Kawahara ,  Riichiro Takemura ,  Takashi Ishigaki ,  Kiyoo Itoh

    IPC分类号： G11C11/16

    CPC分类号： H01L27/228 ,  G11C7/1006 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/5607

    摘要： The disclosed semiconductor recording device achieves multi-valued reading and writing using a spin-injection magnetization-reversal tunneling magnetoresistive element (TMR element). A first current that has at least the same value as that of the element requiring the highest current to reverse the magnetization thereof among a plurality of TMR elements is, in the direction that causes reversal to either a parallel state or an anti-parallel state, applied to a memory cell having the plurality of TMR elements, and then a second current which is in the reverse direction from the first current and of which only the value needed to reverse the magnetoresistance state of at least one TMR element excluding the element requiring the maximum current among the plurality of TMR elements is applied to each, and multi-valued writing is performed.

    摘要翻译： 所公开的半导体记录装置使用自旋注入磁化 - 反转隧道磁阻元件（TMR元件）实现多值读取和写入。 与在多个TMR元件之间需要最大电流以使其磁化反转的元件至少具有相同值的第一电流在引起反向并联状态或反并联状态的方向上， 应用于具有多个TMR元件的存储单元，然后施加与第一电流相反方向的第二电流，并且其中只有反转至少一个TMR元件的磁阻状态所需的值，除了需要 多个TMR元件中的最大电流被施加到每个，并且执行多值写入。

    SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING METHOD
    39.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND DATA PROCESSING METHOD 有权
    半导体存储器件和数据处理方法

    公开(公告)号：US20130033928A1

    公开(公告)日：2013-02-07

    申请号：US13576913

    申请日：2010-02-02

    申请人： Takayuki Kawahara ,  Riichiro Takemura ,  Kazuo Ono ,  Nobuaki Kohinata

    发明人： Takayuki Kawahara ,  Riichiro Takemura ,  Kazuo Ono ,  Nobuaki Kohinata

    IPC分类号： G11C11/16

    CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693

    摘要： Since a nonvolatile RAM allows random reading and writing operations, an erasing mode is unnecessary. From the system side, however, it is desirable to have the erasing mode because of its nonvolatile characteristic. Moreover, the erasing operation is desirably carried out at high speed with low power consumption. Therefore, memory cell arrays COA and DTA containing a plurality of memory cells MC each having a magnetoresistive element are provided, a series of data is written to the memory cell arrays COA and DTA, and at the time of erasing, an erasing operation is carried out by writing predetermined data only to the memory cell array COA.

    摘要翻译： 由于非易失性RAM允许随机读取和写入操作，因此不需要擦除模式。 然而，从系统侧，由于其非易失性特性，期望具有擦除模式。 此外，擦除操作期望以低功耗高速进行。 因此，提供了包含具有磁阻元件的多个存储单元MC的存储单元阵列COA和DTA，将一系列数据写入存储单元阵列COA和DTA，并且在擦除时，进行擦除操作 通过将预定数据仅写入存储单元阵列COA来实现。

    Semiconductor device
    40.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08228724B2

    公开(公告)日：2012-07-24

    申请号：US13345231

    申请日：2012-01-06

    申请人： Riichiro Takemura ,  Kenzo Kurotsuchi ,  Takayuki Kawahara

    发明人： Riichiro Takemura ,  Kenzo Kurotsuchi ,  Takayuki Kawahara

    IPC分类号： G11C11/00

    CPC分类号： H01L47/00 ,  G11C13/0004 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

    摘要： For example, one memory cell is configured using two memory cell transistors and one phase change element by disposing a plurality of diffusion layers in parallel to a bit-line, disposing gates between the diffusion layers so as to cross the bit-line, disposing bit-line contacts and source contacts alternately to the plurality of diffusion layers arranged in a bit-line direction for each diffusion layer, and providing a phase change element on the source contact. Also, the phase change element can be provided on the bit-line contact instead of the source contact. By this means, for example, increase in drivability of the memory cell transistors and reduction in area can be realized.

    摘要翻译： 例如，一个存储单元被配置为使用两个存储单元晶体管和一个相变元件，通过将多个扩散层与位线平行地布置，在扩散层之间设置栅极以跨越位线，布置位 线接触和源触点交替地布置到针对每个扩散层的位线方向上的多个扩散层，以及在源极触点上提供相变元件。 此外，相位元件可以设置在位线触点上而不是源极触点。 通过这种方式，例如，可以实现存储单元晶体管的驱动性的提高和面积的减小。