公开(公告)号：US20120187459A1

公开(公告)日：2012-07-26

申请号：US13010028

申请日：2011-01-20

Applicant: Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

Inventor： Te-Jen Pan ,  Yu-Hsien Lin ,  Hsiang-Ku Shen ,  Wei-Han Fan ,  Yun Jing Lin ,  Yimin Huang ,  Tzu-Chung Wang

IPC: H01L29/772 ,  H01L21/28 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Abstract translation: 描述了一种方法，其包括提供衬底并形成邻接衬底上的栅极结构的第一间隔物材料层。 第二间隔材料层邻近并邻接栅极结构并且覆盖第一间隔物层形成。 然后分别同时蚀刻第一间隔材料层和第二间隔材料层以形成第一和第二间隔物。 在衬底上形成（例如，生长）外延区域，其包括与第一和第二间隔物中的每一个的界面。 随后可以移除第二间隔物，并且保留在器件上的第一间隔物减小ILD间隙填充的纵横比。 第一间隔物的实例组成是SiCN。

公开(公告)号：US20120079827A1

公开(公告)日：2012-04-05

申请号：US13323754

申请日：2011-12-12

Applicant: Yimin HUANG ,  Shaun SULLIVAN ,  Brian FINSTAD ,  Alexander HAPLAU-COLAN

Inventor： Yimin HUANG ,  Shaun SULLIVAN ,  Brian FINSTAD ,  Alexander HAPLAU-COLAN

IPC: F23R3/14 ,  F02C7/12 ,  F02C7/22

CPC classification number: F23R3/14 ,  F23R3/283 ,  F23R3/286 ,  F23R3/46

Abstract: A combustor for a gas turbine engine is disclosed which is able to operate with high combustion efficiency, and low nitrous oxide emissions during gas turbine operations. The combustor consists of a can-type configuration which combusts fuel premixed with air and delivers the hot gases to a turbine. Fuel is premixed with air through a swirler and is delivered to the combustor with a high degree of swirl motion about a central axis. This swirling mixture of reactants is conveyed downstream through a flow path that expands; the mixture reacts, and establishes an upstream central recirculation flow along the central axis. A cooling assembly is located on the swirler co-linear with the central axis in which cooler air is conveyed into the prechamber between the recirculation flow and the swirler surface.

Abstract translation: 公开了一种用于燃气涡轮发动机的燃烧器，其能够在燃气轮机操作期间以高燃烧效率和低氧化亚氮排放进行操作。 燃烧器由罐型构成，其燃烧与空气预混合的燃料并将热气体输送到涡轮机。 燃料通过旋流器与空气预混合并且以围绕中心轴线的高度漩涡运动输送到燃烧器。 反应物的这种旋转混合物通过膨胀的流动路径向下游传送; 混合物反应，并建立沿中心轴的上游中央再循环流。 冷却组件位于与中心轴线共线的旋流器上，其中较冷的空气被输送到再循环流和旋流器表面之间的预燃室中。

公开(公告)号：US07378740B2

公开(公告)日：2008-05-27

申请号：US11196038

申请日：2005-08-02

Applicant: Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

Inventor： Tri-Rung Yew ,  Yimin Huang ,  Water Lur ,  Shih-Wei Sun

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/7681 ,  H01L21/76832 ,  H01L21/76835 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An improved dual damascene structure is provided for use in the wiring-line structures of multi-level interconnects in integrated circuit. In this dual damascene structure, low-K (low dielectric constant) dielectric materials are used to form both the di-electric layers and the etch-stop layers between the metal interconnects in the IC device. With this feature, the dual damascene structure can prevent high parasite capacitance to occur therein that would otherwise cause large RC delay to the signals being transmitted through the metal interconnects and thus degrade the performance of the IC device. With the dual damascene structure, such parasite capacitance can be reduced, thus assuring the performance of the IC device.

Abstract translation: 提供了一种改进的双镶嵌结构，用于集成电路中多级互连的布线结构。 在这种双镶嵌结构中，使用低K（低介电常数）介电材料来形成IC器件中的金属互连之间的二电层和蚀刻停止层。 利用该特征，双镶嵌结构可以防止在其中发生高的寄生电容，否则会对通过金属互连传输的信号造成较大的RC延迟，从而降低IC器件的性能。 利用双镶嵌结构，可以减少这种寄生电容，从而确保IC器件的性能。

公开(公告)号：US06680248B2

公开(公告)日：2004-01-20

申请号：US09991131

申请日：2001-11-20

Applicant: Yimin Huang ,  Tri-Rung Yew

Inventor： Yimin Huang ,  Tri-Rung Yew

IPC: H01L214763

CPC classification number: H01L21/76829 ,  H01L21/76807

Abstract: A method of forming a dual damascene structure comprises the steps of providing a substrate having a first conductive layer formed thereon, and then sequentially forming a first dielectric layer, an anti-reflection layer and a second dielectric layer over the substrate. Next, the first dielectric layer, the anti-reflection layer and the second dielectric layer are patterned to form a first opening that exposes the conductive layer. Thereafter, the second dielectric layer is patterned to form a trench (or second opening) in a position above the first conductive layer. The trench and the first opening together form an opening of the dual damascene structure. Finally, a second conductive material is deposited into the opening and the trench to form conductive lines and the dual damascene structures.

Abstract translation: 形成双镶嵌结构的方法包括以下步骤：提供其上形成有第一导电层的衬底，然后在衬底上顺序形成第一电介质层，抗反射层和第二电介质层。 接下来，对第一电介质层，抗反射层和第二电介质层进行图案化以形成暴露导电层的第一开口。 此后，第二介电层被图案化以在第一导电层上方的位置形成沟槽（或第二开口）。 沟槽和第一开口一起形成双镶嵌结构的开口。 最后，将第二导电材料沉积到开口和沟槽中以形成导电线和双镶嵌结构。

公开(公告)号：US06388326B2

公开(公告)日：2002-05-14

申请号：US09800574

申请日：2001-03-08

Applicant: Hermen Liu ,  Yimin Huang

Inventor： Hermen Liu ,  Yimin Huang

IPC: H01L2328

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/0508 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/48463 ,  H01L2924/0001 ,  H01L2924/01009 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/04941 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00015 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/05541 ,  H01L2224/05005

Abstract: The present invention provides a bonding pad on a semiconductor chip such that peeling of bonding pads during interconnection in the packaging process is avoided. The bonding pad is used to electrically connect an integrated circuit in the semiconductor chip with an external circuit. The semiconductor chip comprises a first dielectric layer positioned in a predetermined area on the surface of the semiconductor chip, a second dielectric layer positioned on the surface of the semiconductor chip outside the predetermined area wherein the first dielectric layer is harder than the second dielectric layer, and a bonding pad positioned on the first dielectric layer for electrically connecting anintegrated circuit (IC) in the semiconductor chip with an external circuit.

Abstract translation: 本发明提供了半导体芯片上的接合焊盘，从而避免了在封装过程中的互连期间剥离焊盘。 焊盘用于将半导体芯片中的集成电路与外部电路电连接。 半导体芯片包括位于半导体芯片的表面上的预定区域中的第一电介质层，位于半导体芯片的表面上的第二电介质层，其中第一电介质层比第二介电层硬， 以及位于第一电介质层上的用于将半导体芯片中的集成电路（IC）电连接到外部电路的接合焊盘。

公开(公告)号：US06352918B1

公开(公告)日：2002-03-05

申请号：US09199877

申请日：1998-11-24

Applicant: Yimin Huang ,  Chih-Chien Liu ,  Tri-Rung Yew

Inventor： Yimin Huang ,  Chih-Chien Liu ,  Tri-Rung Yew

IPC: H01L21311

CPC classification number: H01L21/76802

Abstract: A method of forming an inter-metal interconnection is provided. A substrate is provided. A dielectric layer with a metal plug therein is formed on the substrate. An IMD layer is formed on the dielectric layer. An insulating layer and a PE-oxide layer are formed on the IMD layer. A photolithography and etching process is performed to form a trench in the IMD layer and to expose the metal plug in the dielectric layer. A metal is filled into the trench to electrically connect to the metal plug.

Abstract translation: 提供了形成金属间互连的方法。 提供基板。 在基板上形成有金属塞的电介质层。 在电介质层上形成IMD层。 在IMD层上形成绝缘层和PE-氧化物层。 进行光刻和蚀刻工艺以在IMD层中形成沟槽并露出介电层中的金属插塞。 将金属填充到沟槽中以电连接到金属插头。

公开(公告)号：US06339025B1

公开(公告)日：2002-01-15

申请号：US09304436

申请日：1999-04-03

Applicant: Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

Inventor： Chih-Chien Liu ,  Kun-Chih Wang ,  Wen-Yi Hsieh ,  Yimin Huang

IPC: H01L2144

CPC classification number: H01L21/76886 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76867

Abstract: A method of fabricating a copper capping layer. A silicon rich nitride layer is formed on an exposed copper layer. Since the silicon rich nitride layer has more dangling bonds inside, the silicon in the silicon rich nitride layer easily reacts with the copper and a copper silicide layer is formed between the copper and the silicon rich nitride layer. Therefore, adhesion of the copper and the silicon rich nitride layer can be improved.

Abstract translation: 一种制造铜覆盖层的方法。 在暴露的铜层上形成富氮的氮化物层。 由于富含硅的氮化物层内部具有更多的悬空键，富硅氮化物层中的硅容易与铜反应，并且在铜和富硅氮化物层之间形成铜硅化物层。 因此，可以提高铜和富硅氮化物层的粘合性。

公开(公告)号：US06297561B1

公开(公告)日：2001-10-02

申请号：US09630529

申请日：2000-08-01

Applicant: Hermen Liu ,  Yimin Huang

Inventor： Hermen Liu ,  Yimin Huang

IPC: H01L2348

CPC classification number: H01L24/05 ,  H01L23/3171 ,  H01L24/10 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/451 ,  H01L2224/4807 ,  H01L2224/4845 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00015 ,  H01L2924/00

Abstract: The present invention provides a semiconductor chip. The semiconductor chip comprising an integrated circuit (IC) positioned within the semiconductor chip, and a bonding pad positioned on the surface of the semiconductor chip and electrically connected with the IC. The method comprises using a probe to contact a predetermined testing area on the surface of the bonding pad to electrically test the IC, and forming a passivation layer on the surface of the semiconductor chip to passivate the surface of the semiconductor chip. The testing area of the bonding pad is covered under the passivation layer and the passivation layer comprises an opening positioned on the bonding pad outside the testing area which is used as a connecting area for performing wire bonding or bumping.

Abstract translation: 本发明提供一种半导体芯片。 包括位于半导体芯片内的集成电路（IC）的半导体芯片和位于半导体芯片的表面上且与IC电连接的接合焊盘。 该方法包括使用探针接触焊盘表面上的预定测试区域以对IC进行电测试，以及在半导体芯片的表面上形成钝化层以钝化半导体芯片的表面。 接合焊盘的测试区域被覆​​盖在钝化层下方，并且钝化层包括位于测试区域外的焊盘上的开口，该开口用作用于进行引线接合或凸起的连接区域。

公开(公告)号：US6069066A

公开(公告)日：2000-05-30

申请号：US208025

申请日：1998-12-09

Applicant: Yimin Huang ,  Tri-Rung Yew

Inventor： Yimin Huang ,  Tri-Rung Yew

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/44

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05546 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14

Abstract: A method of forming a bonding pad is provided. A substrate is provided and a multi-metal layer is formed on the substrate. An inter-metal dielectric layer with a trench is formed on the multi-metal layer. A conformal barrier layer is formed on the inter-metal dielectric layer. A first metal layer is formed on the barrier layer to fill a part of the trench. A second metal layer is formed on the first metal layer to fill the trench. A part of the first metal layer and a part of the second metal layer flowing out the trench are removed to expose the inter-metal dielectric layer. A cap layer is formed on the inter-metal dielectric layer. A passivation layer is formed on the cap layer. A part of the passivation and a part of the cap layer are removed to form a bonding pad window by a defined masking layer.

Abstract translation: 提供一种形成接合焊盘的方法。 设置基板，在基板上形成多金属层。 在多金属层上形成具有沟槽的金属间介电层。 在金属间电介质层上形成保形阻挡层。 在阻挡层上形成第一金属层以填充沟槽的一部分。 在第一金属层上形成第二金属层以填充沟槽。 去除第一金属层的一部分和流出沟槽的第二金属层的一部分，以露出金属间介电层。 在金属间介电层上形成盖层。 在盖层上形成钝化层。 通过限定的掩模层去除钝化部分和覆盖层的一部分以形成焊盘窗口。

公开(公告)号：US06027994A

公开(公告)日：2000-02-22

申请号：US102083

申请日：1998-06-22

Applicant: Yimin Huang ,  Tri-Rung Yew

Inventor： Yimin Huang ,  Tri-Rung Yew

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/4763

CPC classification number: H01L21/76808 ,  H01L23/5226 ,  H01L2221/1031 ,  H01L2924/0002

Abstract: A method to fabricate a dual damascene structure in a substrate is disclosed in the present invention. A first silicon oxide layer is deposited over the substrate and a silicon nitride layer is formed on the first silicon oxide layer. The first silicon oxide layer and the silicon nitride layer are etched in order to form a via hole on the substrate. Afterwards, a second silicon oxide layer is deposited to refill into the via hole and to cover the silicon nitride layer. A dry etching process is performed to remove the second silicon oxide layer in the via hole and to form a metal trench in the second silicon oxide layer on the silicon nitride layer and a metal trench in the second silicon oxide layer above the via hole. After the formation of the metal trenches, a portion of the second silicon oxide layer is remained on the sidewalls and the bottom of the via hole. A dry etching process is performed to remove the remaining portion of the second silicon oxide layer. At last, metal material is deposited to refill into the via hole and the metal trench, it is followed by the metal CMP processs to remove the excess metal over the silicon oxide. The dual metal-damascene structure on the substrate is complete.

Abstract translation: 在本发明中公开了一种在衬底中制造双镶嵌结构的方法。 在衬底上沉积第一氧化硅层，在第一氧化硅层上形成氮化硅层。 蚀刻第一氧化硅层和氮化硅层以在基板上形成通孔。 然后，沉积第二氧化硅层以重新填充到通孔中并覆盖氮化硅层。 进行干蚀刻处理以去除通孔中的第二氧化硅层，并且在氮化硅层上的第二氧化硅层中形成金属沟槽，在通孔上方的第二氧化硅层中形成金属沟槽。 在形成金属沟槽之后，第二氧化硅层的一部分残留在通孔的侧壁和底部。 执行干蚀刻处理以去除第二氧化硅层的剩余部分。 最后，沉积金属材料以再填充到通孔和金属沟槽中，之后是金属CMP工艺以除去氧化硅上的多余金属。 基板上的双金属镶嵌结构完整。