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    LOCOS field oxide and field oxide process using silicon nitride spacers
    33.
    发明授权
    LOCOS field oxide and field oxide process using silicon nitride spacers 失效
    使用氮化硅间隔物的LOCOS场氧化物和场氧化物工艺

    公开(公告)号：US5895257A

    公开(公告)日：1999-04-20

    申请号：US691288

    申请日：1996-08-01

    申请人： Chaochieh Tsai ,  Yuan-Chang Huang ,  Juing-Yi Wu ,  Shun-Liang Hsu

    发明人： Chaochieh Tsai ,  Yuan-Chang Huang ,  Juing-Yi Wu ,  Shun-Liang Hsu

    IPC分类号： H01L21/762 ,  H01L21/76

    CPC分类号： H01L21/76202

    摘要： A field oxide region and method of forming a field oxide region using a LOCOS process and nitride spacers formed on the sidewalls of the field oxide regions. During the LOCOS process recesses are formed in the field oxide which result in poor step coverage during successive process steps. Nitride spacers are formed on the sidewalls of the field oxide covering the recesses. The spacers provide a smooth surface over the field oxide and improved step coverage during subsequent process steps.

    摘要翻译： 场氧化物区域和使用LOCOS工艺形成场氧化物区域的方法和形成在场氧化物区域的侧壁上的氮化物间隔物。 在LOCOS过程中，在场氧化物中形成凹陷，这在连续的工艺步骤期间导致差的台阶覆盖。 氮化物间隔物形成在覆盖凹部的场氧化物的侧壁上。 间隔物在场氧化物上提供光滑的表面，并在随后的工艺步骤中改善了台阶覆盖。

    0.3 Micron aperture width patterning process
    34.
    发明授权
    0.3 Micron aperture width patterning process 失效
    0.3微米孔径宽度图案化工艺

    公开(公告)号：US5753418A

    公开(公告)日：1998-05-19

    申请号：US706876

    申请日：1996-09-03

    申请人： Chia Shiung Tsai ,  Yuan-Chang Huang ,  Chen-Hua Yu

    发明人： Chia Shiung Tsai ,  Yuan-Chang Huang ,  Chen-Hua Yu

    IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/311 ,  G03F7/00

    CPC分类号： H01L21/31144 ,  G03F7/091 ,  H01L21/0276 ,  H01L21/31138

    摘要： A method for forming a patterned layer within an integrated circuit. There is first provided a substrate having formed thereover a blanket target layer. There is then formed upon the blanket target layer a blanket focusing layer, where the blanket focusing layer is formed of an organic anti-reflective coating (ARC) material which is susceptible to a reproducible positive taper within a first etch method employed in forming from the blanket focusing layer a patterned focusing layer. The first etch method is a first plasma etch method employing an etchant gas composition comprising carbon tetrafluoride and argon. There is then formed upon the blanket focusing layer a blanket photoresist layer. The blanket photoresist layer is then photoexposed and developed layer to form a patterned photoresist layer. The blanket focusing layer is then etched through the first etch method to form the patterned focusing layer while employing the patterned photoresist layer as a first etch mask layer, where the patterned focusing layer has the reproducible positive taper with respect to the patterned photoresist layer and the blanket target layer. Finally, the blanket target layer is etched through a second etch method to form a patterned target layer while employing the patterned focusing layer as a second etch mask layer, where the patterned target layer has a reproducible second etch bias with respect to the patterned focusing layer, where the reproducible second etch bias does not substantially compensate the reproducible positive taper, and where the width of an aperture within the patterned target layer varies inversely as a function of the thickness of the patterned focusing layer.

    摘要翻译： 一种用于在集成电路内形成图案层的方法。 首先提供了在覆盖目标层之上形成的衬底。 然后在毯子目标层上形成橡皮布聚焦层，其中橡皮布聚焦层由有机抗反射涂层（ARC）材料形成，该有机抗反射涂层（ARC）材料在第一蚀刻方法中易于产生可再现的正锥度， 毯状聚焦层是图案化聚焦层。 第一蚀刻方法是使用包含四氟化碳和氩的蚀刻剂气体组合物的第一等离子体蚀刻方法。 然后在橡皮布聚焦层上形成覆盖光致抗蚀剂层。 然后将覆盖的光致抗蚀剂层照相和显影，以形成图案化的光致抗蚀剂层。 然后通过第一蚀刻方法蚀刻橡皮布聚焦层以形成图案化聚焦层，同时使用图案化的光致抗蚀剂层作为第一蚀刻掩模层，其中图案化的聚光层相对于图案化的光致抗蚀剂层具有可再现的正锥度， 毯子目标层。 最后，通过第二蚀刻方法蚀刻覆盖层目标层以形成图案化目标层，同时使用图案化聚焦层作为第二蚀刻掩模层，其中图案化目标层相对于图案化聚光层具有可再现的第二蚀刻偏置 ，其中可再现的第二蚀刻偏压基本上不补偿可再现的正锥度，并且其中图案化目标层内的孔的宽度作为图案化聚焦层的厚度的函数反向变化。

    Test site and a method of monitoring via etch depths for semiconductor devices
    35.
    发明授权
    Test site and a method of monitoring via etch depths for semiconductor devices 失效
    测试点和通过半导体器件的蚀刻深度监测的方法

    公开(公告)号：US5702956A

    公开(公告)日：1997-12-30

    申请号：US703086

    申请日：1996-08-26

    申请人： Shu-Lan Ying ,  Yuan-Chang Huang ,  Jue-Jye Chen ,  Yuh-Jier Mii

    发明人： Shu-Lan Ying ,  Yuan-Chang Huang ,  Jue-Jye Chen ,  Yuh-Jier Mii

    IPC分类号： H01L21/66 ,  H01L23/544

    CPC分类号： H01L22/34 ,  H01L22/12

    摘要： The present invention provides a test site on a product wafer for measuring via etch depth and a method of monitoring the depth of the vias using the test site. A substrate is provided having a test site area and a circuit area. A test site via is formed in the test site area. The test site via is used in measuring the depth of the insulating layers remaining in a test site via and the depth of the test site via. The measurements are taking using an in-line non-destructible measurement tool, such as an ellipsometer or spectrophotometer. The test site is specifically designed to be large enough to have the via depth measured by an in-line measuring tool. The depth of the oxide remaining in the test site via is measured after the via etch and is correlated to the amount of titanium nitride removed from the tops of the metal lines in the circuit areas. The via etch process is then adjusted to center the via etch at the optimum point to ensure that enough the vias are deep enough without removing too much of the top barrier layer (e.g., titanium nitride) film over the metal lines.

    摘要翻译： 本发明提供了用于通过蚀刻深度测量的产品晶片上的测试位置以及使用测试部位监测通孔的深度的方法。 提供具有测试位置区域和电路区域的衬底。 试验场地通过形成试验场地。 测试点通孔用于测量残留在测试部位的绝缘层的深度和测试部位通孔的深度。 测量正在使用在线不可破坏的测量工具，例如椭偏仪或分光光度计。 测试地点专门设计为足够大，以便通过在线测量工具测量通孔深度。 在通孔蚀刻之后测量残留在测试部位通孔中的氧化物的深度，并且与从电路区域中的金属线的顶部去除的氮化钛的量相关。 然后调整通孔蚀刻工艺以使通孔蚀刻在最佳点处居中，以确保足够的通孔足够深，而不会在金属线上去除太多的顶部阻挡层（例如氮化钛）膜。

    Method to remove residue of metal etch
    36.
    发明授权
    Method to remove residue of metal etch 失效
    去除金属蚀刻残留物的方法

    公开(公告)号：US5641382A

    公开(公告)日：1997-06-24

    申请号：US590024

    申请日：1996-02-02

    申请人： Tsu Shih ,  Chih-Chien Hung ,  Yuan-Chang Huang

    发明人： Tsu Shih ,  Chih-Chien Hung ,  Yuan-Chang Huang

    IPC分类号： H01L21/3213 ,  H01L21/00

    CPC分类号： H01L21/32137

    摘要： This invention provides a method for removing metal etch residue of silicon nodules, resulting from a small percentage of silicon in the metal, without causing overetch damage to the photoresist pattern, the metal electrode pattern, or to dielectric layers. The metal conductor layer is partially etched leaving from 20 to 80 percent of the original thickness. Any residue of silicon nodules formed during this partial etching is then removed using ion bombardment. The remainder of the metal conductor layer is then etched. A short overetch period is used to remove any remaining residue of silicon nodules. The overetch period is short and there is no deterioration of the photoresist or exposed edges of the electrode pattern.

    摘要翻译： 本发明提供一种从金属中少量的硅产生的硅结节的金属蚀刻残留物的去除，而不会对光致抗蚀剂图案，金属电极图案或介电层造成过蚀刻损伤的方法。 部分蚀刻金属导体层，留下原始厚度的20％至80％。 然后使用离子轰击去除在该部分蚀刻期间形成的任何硅结渣残留物。 然后蚀刻金属导体层的其余部分。 使用短的过氧化物周期来去除任何剩余的硅结节残留物。 过氧化物周期短，并且电极图案的光致抗蚀剂或暴露的边缘没有劣化。

    In situ hot bake treatment that prevents precipitate formation after a contact layer etch back step
    37.
    发明授权
    In situ hot bake treatment that prevents precipitate formation after a contact layer etch back step 失效
    在接触层回蚀步骤之后防止沉淀物形成的原位热烘烤处理

    公开(公告)号：US5554563A

    公开(公告)日：1996-09-10

    申请号：US416163

    申请日：1995-04-04

    申请人： Po-Tao Chu ,  Kuang-Hui Chang ,  Yuan-Chang Huang

    发明人： Po-Tao Chu ,  Kuang-Hui Chang ,  Yuan-Chang Huang

    IPC分类号： H01L21/321 ,  H01L21/768 ,  H01L21/28

    CPC分类号： H01L21/321 ,  H01L21/76838

    摘要： A process for preventing the formation of precipitates on a substrate surface containing titanium after a contact layer (e.g., tungsten layer) etch back. The process involves removing the precursor chemicals of the precipitate. With the invention, the precursor are removed by baking the substrate at a temperature of approximately 120.degree. C. for approximately 80 seconds. Preferably, the baking process is performed in situ by a halogen lamp mounted on the exit loading dock of the etcher thereby not impacting the wafer throughput of the etcher.

    摘要翻译： 在接触层（例如钨层）回蚀后，在含有钛的基板表面上防止析出物形成的方法。 该方法包括去除沉淀物的前体化学物质。 利用本发明，通过在大约120℃的温度下烘烤基底来除去前体约80秒。 优选地，通过安装在蚀刻器的出口加载基座上的卤素灯在原位进行烘焙处理，从而不影响蚀刻器的晶片生产量。