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    System on a chip with fast wake from sleep
    32.
    发明授权
    System on a chip with fast wake from sleep 有权

    公开(公告)号：US10915160B2

    公开(公告)日：2021-02-09

    申请号：US16746121

    申请日：2020-01-17

    Applicant: Apple Inc.

    Inventor： Anand Dalal ,  Joshua P. de Cesare

    IPC: G06F1/32 ,  G06F9/44 ,  G06F9/445 ,  G06F1/3287 ,  G06F9/4401 ,  G06F1/3209 ,  G06F1/3215 ,  G06F1/3231 ,  G06F1/3293

    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

    Access permissions modification
    35.
    发明授权
    Access permissions modification 有权

    公开(公告)号：US09852084B1

    公开(公告)日：2017-12-26

    申请号：US15017427

    申请日：2016-02-05

    Applicant: Apple Inc.

    Inventor： Peter G. Soderquist ,  Pradeep Kanapathipillai ,  Bernard J. Semeria ,  Joshua P. de Cesare ,  David J. Williamson ,  Gerard R. Williams, III

    IPC: G06F12/14 ,  G06F12/1009

    CPC classification number: G06F12/1483 ,  G06F12/1009 ,  G06F2212/1052

    Abstract: Systems, apparatuses, and methods for modifying access permissions in a processor. A processor may include one or more permissions registers for managing access permissions. A first permissions register may be utilized to override access permissions embedded in the page table data. A plurality of bits from the page table data may be utilized as an index into the first permissions register for the current privilege level. An attribute field may be retrieved from the first permissions register to determine the access permissions for a given memory request. A second permissions register may also be utilized to set the upper and lower boundary of a region in physical memory where the kernel is allowed to execute. A lock register may prevent any changes from being made to the second permissions register after the second permissions register has been initially programmed.

    Methods and systems for time keeping in a data processing system
    36.
    发明授权
    Methods and systems for time keeping in a data processing system 有权

    公开(公告)号：US09632563B2

    公开(公告)日：2017-04-25

    申请号：US14159705

    申请日：2014-01-21

    Applicant: Apple Inc.

    Inventor： Joshua P. de Cesare ,  Bernard Joseph Semeria ,  Michael John Smith

    IPC: G06F13/36 ,  G06F1/32 ,  G06F9/48 ,  G06F13/24

    CPC classification number: G06F1/3287 ,  G06F9/4825 ,  G06F13/24 ,  G06F13/36 ,  Y02D10/14 ,  Y02D10/24

    Abstract: Data processing systems with interrupts and methods for operating such data processing systems and machine readable media for causing such methods and containing executable program instructions. In one embodiment, an exemplary data processing system includes a processing system, an interrupt controller coupled to the processing system and a timer circuit which is coupled to the interrupt controller. The interrupt controller is configured to provide a first interrupt signal and a second interrupt signal to the processing system. The processing system is configured to maintain a data structure (such as, e.g., a list) of time-related events for a plurality of processes, and the processing system is configured to calise the entry of a value, representing a period of time, into the timer circuit. The timer circuit is configured to cause an assertion of the first interrupt signal in response to an expiration of the time period.

    System on a Chip with Always-On Processor
    38.
    发明申请
    System on a Chip with Always-On Processor 审中-公开
    带有始终处理器的芯片上的系统

    公开(公告)号：US20150346001A1

    公开(公告)日：2015-12-03

    申请号：US14458885

    申请日：2014-08-13

    Applicant: Apple Inc.

    Inventor： Brijesh Tripathi ,  Shane J. Keil ,  Manu Gulati ,  Jung Wook Cho ,  Erik P. Machnicki ,  Gilbert H. Herbeck ,  Timothy J. Millet ,  Joshua P. de Cesare ,  Anand Dalal

    IPC: G01D9/00 ,  G06F1/32 ,  G06F13/16

    CPC classification number: G01D9/00 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/3293 ,  G06F13/1689 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

    Abstract translation: 在一个实施例中，芯片上的系统（SOC）包括当SOC的其余部分断电时保持供电的组件。 该组件可以包括用于从各种设备传感器捕获数据的传感器捕获单元，并且可以对所捕获的传感器数据进行过滤。 响应于过滤，组件可以唤醒SOC的剩余部分以允许处理。 组件可以存储可编程配置数据，与SOC最近断电时的状态相匹配，用于SOC的其他组件，以便在唤醒后重新编程它们。 在一些实施例中，组件可以被配置为唤醒SOC内的存储器控​​制器和到存储器控制器的路径，以便将数据写入存储器。 SOC的其余部分可能仍然断电。

    REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK
    39.
    发明申请
    REDUCING LATENCY IN A PERIPHERAL COMPONENT INTERCONNECT EXPRESS LINK 有权
    在外围组件互联互通链接中减少延迟

    公开(公告)号：US20140082242A1

    公开(公告)日：2014-03-20

    申请号：US13622266

    申请日：2012-09-18

    Applicant: APPLE INC.

    Inventor： Michael W. Murphy ,  Joshua P. de Cesare ,  Timothy R. Paaske

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

    Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

    Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。

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