公开(公告)号：US09779468B2

公开(公告)日：2017-10-03

申请号：US14816508

申请日：2015-08-03

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Arthur L. Spence ,  Gurjeet S. Saund ,  Robert P. Esser

IPC: G06T1/20 ,  G06F9/52 ,  G06F9/48 ,  G09G5/36 ,  G09G5/00 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4893 ,  G06F9/52 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G2360/08 ,  Y02D10/24

Abstract: An embodiment of a system may include a plurality of media units, a processor, and circuitry. Each media unit may be configured to execute one or more commands to process a display image. The processor may be configured to store a plurality of media processing commands in a queue. The circuitry may be configured to retrieve a first media processing command from the queue and send the first media processing command to a first media unit. The circuitry may also be configured to retrieve a second media processing from the queue and send the second media processing command to a second media unit in response to receiving an interrupt from the first media unit. The circuitry may then copy data from the first media unit to the second media unit in response to receiving the interrupt from the first media unit.

公开(公告)号：US09344626B2

公开(公告)日：2016-05-17

申请号：US14082390

申请日：2013-11-18

Applicant: Apple Inc.

Inventor： D. Amnon Silverstein ,  Shun Wai Go ,  Suk Hwan Lim ,  Timothy J. Millet ,  Ting Chen ,  Bin Ni

IPC: H04N7/01 ,  H04N5/232 ,  H04N9/87 ,  H04N1/21

CPC classification number: H04N5/23245 ,  H04N1/212 ,  H04N5/23216 ,  H04N5/23232 ,  H04N5/23293 ,  H04N7/0122 ,  H04N9/87

Abstract: In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution 16×9 frames in the video sequence, and may capture the nearest higher resolution, 4×3 frame when the user indicates the capture of a still frame. Alternatively, the device may display 16×9 frames in the video sequence, and then expand to 4×3 frames when a shutter button is pressed. The device may capture the still frame and return to the 16×9 video frames responsive to a release of the shutter button.

Abstract translation: 在一个实施例中，电子设备可以被配置为在视频捕获期间捕获静止帧，但是可以以比4×3宽高比和高于16×9宽高比视频帧的分辨率捕获静止帧。 该装置可以在视频序列中交错高分辨率，4×3帧和较低分辨率的16×9帧，并且当用户指示拍摄静止帧时可以捕获最近的较高分辨率，4×3帧。 或者，设备可以在视频序列中显示16×9帧，然后当按下快门按钮时，扩展为4×3帧。 该装置可以捕获静止帧并响应于快门按钮的释放而返回到16×9视频帧。

公开(公告)号：US09336563B2

公开(公告)日：2016-05-10

申请号：US14163326

申请日：2014-01-24

Applicant: Apple Inc.

Inventor： Joseph P. Bratt ,  Peter F. Holland ,  Shing Horng Choo ,  Timothy J. Millet ,  Brijesh Tripathi

IPC: G09G5/39 ,  G06T1/60

CPC classification number: G06T1/60 ,  G09G5/39

Abstract: A graphics system may include a display pipe with a buffer configured to store pixels to be processed by a display controller for displaying on a display device, with a buffer control circuit coupled to the buffer to supply pixels to the display controller. When the buffer control circuit detects an underrun of the buffer responsive to the display controller attempting to read pixels from the buffer that have not yet been written to the buffer, the buffer control circuit may supply an underrun pixel to the display. The underrun pixel may be selected from a set of previously stored set of underrun pixels, which may include a most recent valid pixel read by the display controller. A read pointer representative of the location in the buffer from where the display controller is currently attempting to read may be advanced even when an underrun condition occurs. The underrun pixel may be supplied to the display controller until the underrun has been resolved, at which point the most recent valid pixel read from the buffer may be supplied to the display controller.

Abstract translation: 图形系统可以包括具有缓冲器的显示管道，缓冲器被配置为存储要由显示控制器处理的像素，用于在显示设备上显示，缓冲器控制电路耦合到缓冲器以向显示控制器提供像素。 当缓冲器控制电路响应于显示控制器尝试读取尚未写入缓冲器的缓冲器的像素时，缓冲器控制电路检测到欠载，缓冲器控制电路可以向显示器提供欠载像素。 欠载像素可以从先前存储的欠载像素组中选择，其可以包括由显示控制器读取的最新有效像素。 即使在出现欠载条件的情况下，代表显示控制器当前尝试读取的缓冲器中的位置的读取指针也可以被提前。 欠载像素可以被提供给显示控制器，直到欠载已被解析为止，此时从缓冲器读取的最新的有效像素可以被提供给显示控制器。

公开(公告)号：US20160091954A1

公开(公告)日：2016-03-31

申请号：US14499807

申请日：2014-09-29

Applicant: Apple Inc.

Inventor： Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Erik P. Machnicki ,  Keith Cox ,  Timothy J. Millet

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/172

Abstract: Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

Abstract translation: 公开了允许调整计算系统的性能设置的方法的实施例。 一个或多个功能单元可以包括多个监视器电路，每个监视器电路可以被配置为监视对应功能单元的给定操作参数。 在检测到与所监视的操作参数有关的事件时，监视器电路可产生中断。 响应于中断，处理器可以调整计算系统的一个或多个性能设置。

公开(公告)号：US20160065969A1

公开(公告)日：2016-03-03

申请号：US14474114

申请日：2014-08-30

Applicant: Apple Inc.

Inventor： Joseph J. Cheng ,  Timothy J. Millet ,  Shun Wai Go ,  Guy Cote

IPC: H04N19/176 ,  H04N19/182 ,  H04N19/46 ,  H04N19/172

CPC classification number: H04N19/176 ,  G06F9/461 ,  G06F9/4818 ,  H04N19/127 ,  H04N19/129 ,  H04N19/172 ,  H04N19/174 ,  H04N19/182 ,  H04N19/40 ,  H04N19/42 ,  H04N19/46

Abstract: A context switching method for video encoders that enables higher priority video streams to interrupt lower priority video streams. A high priority frame may be received for processing while another frame is being processed. The pipeline may be signaled to perform a context stop for the current frame. The pipeline stops processing the current frame at an appropriate place, and propagates the stop through the stages of the pipeline and to a transcoder through DMA. The stopping location is recorded. The video encoder may then process the higher-priority frame. When done, a context restart is performed and the pipeline resumes processing the lower-priority frame beginning at the recorded location. The transcoder may process data for the interrupted frame while the higher-priority frame is being processed in the pipeline, and similarly the pipeline may begin processing the lower-priority frame after the context restart while the transcoder completes processing the higher-priority frame.

Abstract translation: 一种视频编码器的上下文切换方法，其使得较高优先级的视频流能够中断较低优先级的视频流。 当处理另一帧时，可以接收高优先级帧以进行处理。 可以用信号通知流水线以执行当前帧的上下文停止。 流水线在适当的位置停止处理当前帧，并通过流水线传播停止点，并通过DMA传播到代码转换器。 记录停止位置。 视频编码器然后可以处理较高优先级的帧。 完成后，执行上下文重新启动，并且流水线从记录的位置恢复处理较低优先级的帧。 代码转换器可以在流水线中处理较高优先级帧的同时处理中断帧的数据，类似地，当代码转换器完成处理较高优先级帧时，流水线可以在上下文重新启动之后开始处理较低优先级的帧。

公开(公告)号：US09274953B2

公开(公告)日：2016-03-01

申请号：US14611423

申请日：2015-02-02

Applicant: Apple Inc.

Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

公开(公告)号：US20150134331A1

公开(公告)日：2015-05-14

申请号：US14109101

申请日：2013-12-17

Applicant: Apple Inc.

Inventor： Timothy J. Millet ,  Manu Gulati ,  Michael F. Culbert

IPC: G10L15/06 ,  G10L19/26

CPC classification number: G10L15/28 ,  G06F1/32 ,  G06F1/3228 ,  G06F1/3287 ,  G06F3/165 ,  G10L15/22 ,  G10L25/48 ,  G10L2015/088 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个CPU，存储器控制器和被配置为当SOC的其余部分断电时保持通电的电路。 电路可以被配置为从麦克风接收音频样本，并且将这些音频样本与预定模式匹配，以检测来自包括SOC的设备的用户的可能命令。 响应于检测到预定模式，电路可以使存储器控制器上电，使得音频样本可以存储在与存储器控制器耦合到的存储器中。 该电路还可能导致CPU上电和初始化，并且操作系统（OS）可能引导。 在CPU正在初始化并且OS正在引导的时间内，电路和存储器可能正在捕获音频样本。

公开(公告)号：US08977818B2

公开(公告)日：2015-03-10

申请号：US14032405

申请日：2013-09-20

Applicant: Apple Inc.

Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC: G06F12/00 ,  G06F12/12 ,  G06F12/08

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。

公开(公告)号：US08959369B2

公开(公告)日：2015-02-17

申请号：US14149922

申请日：2014-01-08

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Jung Wook Cho ,  Toshinari Takayanagi ,  Timothy J. Millet

IPC: G06F1/00 ,  G06F1/32 ,  G09G3/18 ,  G11C5/14 ,  H04M1/00 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

公开(公告)号：US20140025900A1

公开(公告)日：2014-01-23

申请号：US14032405

申请日：2013-09-20

Applicant: Apple Inc.

Inventor： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC: G06F12/12

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

Abstract: In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

Abstract translation: 在一个实施例中，描绘为透明和非透明部分的存储器。 透明部分可以由耦合到存储器的控制单元以及对应的标签存储器来控制。 非透明部分可以通过经由输入地址直接访问不透明部分来进行软件控制。 在一个实施例中，存储器可以包括解码器，其被配置为对该地址进行解码并选择透明部分或非透明部分中的位置。 每个请求可以包括将该请求标识为透明或不透明的不透明属性。 在一个实施例中，透明部分的尺寸可以是可编程的。 基于指示透明的非透明属性，解码器可以基于大小来选择性地屏蔽地址的位，以确保解码器仅选择透明部分中的位置。