STRUCTURE FOR III-V DEVICES ON SILICON
    33.
    发明申请
    STRUCTURE FOR III-V DEVICES ON SILICON 有权
    硅的III-V器件的结构

    公开(公告)号:US20140357057A1

    公开(公告)日:2014-12-04

    申请号:US14287927

    申请日:2014-05-27

    Abstract: Embodiments described herein relate to a structure for III-V devices on silicon. A Group IV substrate is provided and a III-V structure may be formed thereon. The III-V structure generally comprises one or more buffer layers and a channel layer disposed on the one or more buffer layers. The one or more buffer layers may be selected to provide optimal microelectronic device properties, such as minimal defects, reduced charge accumulation, and reduced current leakage.

    Abstract translation: 本文描述的实施例涉及硅上III-V器件的结构。 提供IV族基板,并且可以在其上形成III-V结构。 III-V结构通常包括一个或多个缓冲层和设置在一个或多个缓冲层上的沟道层。 可以选择一个或多个缓冲层以提供最佳的微电子器件性质,例如最小的缺陷,减少的电荷累积和减少的电流泄漏。

    METHOD AND APPARATUS FOR WAFER OUTGASSING CONTROL

    公开(公告)号:US20190172728A1

    公开(公告)日:2019-06-06

    申请号:US16172266

    申请日:2018-10-26

    Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.

    INTEGRATED SYSTEM AND METHOD FOR SOURCE/DRAIN ENGINEERING

    公开(公告)号:US20190035623A1

    公开(公告)日:2019-01-31

    申请号:US16148430

    申请日:2018-10-01

    Abstract: Implementations described herein generally provide a method of processing a substrate. Specifically, the methods described are used for cleaning and etching source/drain regions on a silicon substrate in preparation for precise Group IV source/drain growth in semiconductor devices. Benefits of this disclosure include precise fin size control in devices, such as 10 nm FinFET devices, and increased overall device yield. The method of integrated clean and recess includes establishing a low pressure processing environment in the processing volume, and maintaining the low pressure processing environment while flowing a first gas over a substrate in a processing volume, depositing a salt on the substrate, heating the processing volume to greater than 90° C., purging the processing volume with a second inert gas, and recessing a source/drain region disposed on the substrate.

    METHOD AND APPARATUS FOR WAFER OUTGASSING CONTROL

    公开(公告)号:US20180082874A1

    公开(公告)日:2018-03-22

    申请号:US15267232

    申请日:2016-09-16

    CPC classification number: H01L21/67 H01L21/673 H01L21/67393 H01L21/677

    Abstract: Embodiments disclosed herein generally relate to apparatus and methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a substrate after a Si:As process has been performed on a substrate, and prior to additional processing. The apparatus includes a purge station including an enclosure, a gas supply coupled to the enclosure, an exhaust pump coupled to the enclosure, a first purge gas port formed in the enclosure, a first channel operatively connected to the gas supply at a first end and to the first purge gas port at a second end, a second purge gas port formed in the enclosure, and a second channel operatively connected to the second purge gas port at a third end and to the exhaust pump at a fourth end. The first channel includes a particle filter, a heater, and a flow controller. The second channel includes a dry scrubber.

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