公开(公告)号：US20200013629A1

公开(公告)日：2020-01-09

申请号：US16468258

申请日：2017-12-08

Applicant: ASM IP Holding B.V.

Inventor： David Kurt de Roest ,  Werner Knaepen ,  Krzysztof Kachel

IPC: H01L21/3065 ,  H01L21/02 ,  H01L21/324

Abstract: An apparatus and a method for forming a structure within a semiconductor processing apparatus are disclosed. The apparatus includes a first reaction chamber, the first reaction chamber configured to hold at least one substrate having a first layer. The apparatus also includes a precursor delivery system configured to perform an infiltration by sequentially pulsing a first precursor and a second precursor on the substrate. The apparatus may also include a first removal system configured for removing at least a portion of the first layer disposed on the substrate while leaving an infiltrated material, wherein the infiltration and the removing at least a portion of the first layer take place within the same semiconductor processing apparatus. A method of forming a structure within a semiconductor processing apparatus is also disclosed, the method including providing a substrate for processing in a reaction chamber, the substrate having a first layer disposed on the substrate. The method may also include performing a first layer infiltration by sequentially pulsing a first precursor and a second precursor on the substrate, wherein an infiltrated material forms in the first layer from the reaction of the first precursor and the second precursor. The method may also include removing at least a portion of the first layer disposed on the substrate after performing the infiltration, wherein the infiltration and the removing at least a portion of the first layer take place with the same semiconductor processing apparatus.

公开(公告)号：US20190301014A1

公开(公告)日：2019-10-03

申请号：US15940729

申请日：2018-03-29

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Cornelis Thaddeus Herbschleb ,  Werner Knaepen ,  Bert Jongbloed ,  Steven Van Aerde ,  Kelly Houben ,  Theodorus Oosterlaken ,  Chris de Ridder ,  Lucian Jdira

IPC: C23C16/458 ,  C23C16/56 ,  C23C16/50 ,  C23C16/48 ,  C23C16/455

Abstract: The invention relates to a substrate processing apparatus comprising a reaction chamber provided with a substrate rack for holding a plurality of substrates in the reaction chamber. The substrate rack may have a plurality of spaced apart substrate holding provisions configured to hold the plurality of substrates. The apparatus may have an illumination system constructed and arranged to irradiate radiation with a range from 100 to 500 nanometers onto a top surface of the substrates.

公开(公告)号：US20190066997A1

公开(公告)日：2019-02-28

申请号：US15690017

申请日：2017-08-29

Applicant: ASM IP Holding B.V.

Inventor： Arjen Klaver ,  Werner Knaepen ,  Lucian Jdira ,  Gido van der Star ,  Ruslan Kvetny

IPC: H01L21/02 ,  C23C16/52 ,  C23C16/44 ,  C23C16/455

Abstract: There is provided a method and apparatus for forming a layer, by sequentially repeating a layer deposition cycle to process a substrate disposed in a reaction chamber. The deposition cycle comprising: supplying a first precursor into the reaction chamber for a first pulse period; supplying a second precursor into the reaction chamber for a second pulse period. At least one of the first and second precursors may be supplied into the reaction chamber for a pretreatment period longer than the first or second pulse period before sequentially repeating the deposition cycles.

公开(公告)号：US20180286679A1

公开(公告)日：2018-10-04

申请号：US15476752

申请日：2017-03-31

Applicant: ASM IP Holding B.V.

Inventor： Kelly Houben ,  Steven R.A. Van Aerde ,  Maarten Stokhof ,  Bert Jongbloed ,  Dieter Pierreux ,  Werner Knaepen

IPC: H01L21/033

CPC classification number: H01L21/0337

Abstract: The invention relates to a method of forming a semiconductor device by patterning a substrate by providing an amorphous silicon layer on the substrate and forming a hard mask layer on the amorphous silicon layer. The amorphous silicon layer is provided with an anti-crystallization dopant to keep the layer amorphous at increased temperatures (relative to not providing the anti-crystallization dopant). The hard mask layer may comprise silicon and nitrogen.

公开(公告)号：US09916980B1

公开(公告)日：2018-03-13

申请号：US15380895

申请日：2016-12-15

Applicant: ASM IP Holding B.V.

Inventor： Werner Knaepen ,  Jan Willem Maes ,  Bert Jongbloed ,  Krzysztof Kamil Kachel ,  Dieter Pierreux ,  David Kurt De Roest

IPC: H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  C23C16/045 ,  C23C16/45525

Abstract: A method of forming a layer on a substrate is provided by providing the substrate with a hardmask material. The hardmask material is infiltrated with infiltration material during N infiltration cycles by: a) providing a first precursor to the hardmask material on the substrate in the reaction chamber for a first period T1; b) removing a portion of the first precursor for a second period T2; and, c) providing a second precursor to the hardmask material on the substrate for a third period T3, allowing the first and second precursor to react with each other forming the infiltration material.

公开(公告)号：US20170213732A1

公开(公告)日：2017-07-27

申请号：US15413848

申请日：2017-01-24

Applicant: ASM IP Holding B.V.

Inventor： Dieter Pierreux ,  Werner Knaepen ,  Bert Jongbloed

IPC: H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/02183 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/31111 ,  H01L21/31122 ,  H01L21/31144

Abstract: An etch stop layer comprises a metal oxide comprising a metal selected from the group consisting of metals of Group 4 of the periodic table, metals of Group 5 of the periodic table, metals of Group 6 of the periodic table, and yttrium. The metal oxide forms exceptionally thin layers that are resiatant to ashing and HF exposure. Subjecting the etch stop layer to both ashing and HF etch processes removes less than 0.3 nm of the thickness of the etch stop layer, and more preferably less than 0.25 nm. The etch stop layer may be thin and may have a thickness of about 0.5-2 nm. In some embodiments, the etch stop layer comprises tantalum oxide (TaO).

公开(公告)号：US09576790B2

公开(公告)日：2017-02-21

申请号：US14686595

申请日：2015-04-14

Applicant: ASM IP HOLDING B.V.

Inventor： Viljami J. Pore ,  Yosuke Kimura ,  Kunitoshi Namba ,  Wataru Adachi ,  Hideaki Fukuda ,  Werner Knaepen ,  Dieter Pierreux ,  Bert Jongbloed

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/30 ,  C23C16/32 ,  C23C16/455 ,  H01L21/311

CPC classification number: H01L21/02112 ,  C23C16/045 ,  C23C16/30 ,  C23C16/32 ,  C23C16/45523 ,  C23C16/45525 ,  C23C16/45531 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/2254 ,  H01L21/31111

Abstract: Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. One or more of the boron and carbon containing films can have a thickness of less than about 30 angstroms. Methods of doping a semiconductor substrate are provided. Doping a semiconductor substrate can include depositing a boron and carbon film over the semiconductor substrate by exposing the substrate to a vapor phase boron precursor at a process temperature of about 300° C. to about 450° C., where the boron precursor includes boron, carbon and hydrogen, and annealing the boron and carbon film at a temperature of about 800° C. to about 1200° C.

Abstract translation: 提供了沉积硼和碳的膜的方法。 在一些实施例中，提供了沉积具有所需性质（诸如保形性和蚀刻速率）的B，C膜的方法。 一种或多种含硼和/或碳的前体可以在低于约400℃的温度下在基材上分解。含硼和碳的一种或多种膜可以具有小于约30埃的厚度。 提供掺杂半导体衬底的方法。 掺杂半导体衬底可以包括通过在大约300℃至大约450℃的工艺温度下将衬底暴露于气相硼前体而在半导体衬底上沉积硼和碳膜，其中硼前体包括硼， 碳和氢，并在约800℃至约1200℃的温度下退火硼和碳膜。

公开(公告)号：US20240384411A1

公开(公告)日：2024-11-21

申请号：US18788528

申请日：2024-07-30

Applicant: ASM IP Holding B.V.

Inventor： Kornelius Haanstra ,  Lucian C. Jdira ,  Chris G.M. de Ridder ,  Robin Roelofs ,  Werner Knaepen ,  Herbert Terhorst

IPC: C23C16/455 ,  C23C16/458 ,  H01L21/673 ,  H01L21/687

Abstract: A substrate processing apparatus having a tube, a closed liner lining the interior surface of the tube, a plurality of gas injectors to provide a gas to an inner space of the liner, and, a gas exhaust duct to remove gas from the inner space is disclosed. The liner may have a substantially cylindrical wall delimited by a liner opening at a lower end and being substantially closed for gases above the liner opening. The apparatus may have a boat constructed and arranged moveable into the inner space via the liner opening and provided with a plurality of substrate holders for holding a plurality of substrates over a substrate support length in the inner space. Each of the gas injectors may have a single exit opening at the top and the exit openings of the plurality of injectors are substantially equally divided over the substrate support length.

公开(公告)号：US11990333B2

公开(公告)日：2024-05-21

申请号：US18208398

申请日：2023-06-12

Applicant: ASM IP Holding B.V.

Inventor： Viljami Pore ,  Werner Knaepen ,  Bert Jongbloed ,  Dieter Pierreux ,  Gido van Der Star ,  Toshiya Suzuki

IPC: H01L21/02 ,  C23C16/04 ,  C23C16/455 ,  C23C16/50 ,  H01L21/762

CPC classification number: H01L21/0228 ,  C23C16/045 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/45536 ,  C23C16/50 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/76224

Abstract: There is provided a method of filling one or more gaps by providing the substrate in a reaction chamber and introducing a first reactant to the substrate with a first dose, thereby forming no more than about one monolayer by the first reactant on a first area; introducing a second reactant to the substrate with a second dose, thereby forming no more than about one monolayer by the second reactant on a second area of the surface, wherein the first and the second areas overlap in an overlap area where the first and second reactants react and leave an initially unreacted area where the first and the second areas do not overlap; and, introducing a third reactant to the substrate with a third dose, the third reactant reacting with the first or second reactant remaining on the initially unreacted area.

公开(公告)号：US11970766B2

公开(公告)日：2024-04-30

申请号：US18097559

申请日：2023-01-17

Applicant: ASM IP Holding B.V.

Inventor： Ivo Johannes Raaijmakers ,  Jan Willem Maes ,  Werner Knaepen ,  Krzysztof Kamil Kachel

IPC: C23C16/04 ,  C23C16/44 ,  C23C16/448 ,  C23C16/455 ,  C23C16/46 ,  C23C16/52 ,  G03F7/20 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033

CPC classification number: C23C16/045 ,  C23C16/4408 ,  C23C16/4412 ,  C23C16/4485 ,  C23C16/45523 ,  C23C16/45527 ,  C23C16/45544 ,  C23C16/45561 ,  C23C16/46 ,  C23C16/52 ,  G03F7/2004 ,  H01L21/02205 ,  H01L21/0228 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0273

Abstract: Examples of the disclosure relate to a sequential infiltration synthesis apparatus comprising:



a reaction chamber constructed and arranged to accommodate at least one substrate;
a first precursor flow path to provide the first precursor to the reaction chamber when a first flow controller is activated;
a second precursor flow path to provide a second precursor to the reaction chamber when a second flow controller is activated;
a removal flow path to allow removal of gas from the reaction chamber;
a removal flow controller to create a gas flow in the reaction chamber to the removal flow path
when the removal flow controller is activated; and,
a sequence controller operably connected to the first, second and removal flow controllers and the sequence controller being programmed to enable infiltration of an infiltrateable material provided on the substrate in the reaction chamber. The apparatus may be provided with a heating system.