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公开(公告)号：US20210358540A1
公开(公告)日：2021-11-18
申请号：US16875281
申请日：2020-05-15
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl , Kedarnath Balakrishnan , Jing Wang , Guanhao Shen
IPC: G11C11/406
Abstract: A memory controller interfaces with a dynamic random access memory (DRAM) over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
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公开(公告)号：US11176986B2
公开(公告)日：2021-11-16
申请号：US16730086
申请日：2019-12-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl , Naveen Davanam , Oswin E. Housty
IPC: G11C7/00 , G11C11/406 , G06F12/02 , G06F13/40 , G06F13/16 , G06F1/3234
Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.
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公开(公告)号：US10067718B2
公开(公告)日：2018-09-04
申请号：US15274178
申请日：2016-09-23
Applicant: Advanced Micro Devices, Inc.
Inventor： Glennis Eliagh Covington , Kevin M. Brandl , Nienchi Hu , Shannon T. Kesner
Abstract: Dynamic random access memory (DRAM) chips in memory modules include multi-purpose registers (MPRs) having pre-defined data patterns which, when selected, are accessed with read commands and output on data lines for performing read training. The MPRs are accessed by issuing read commands to specific register addresses to request reads from specific MPR locations. In some embodiments, read training for memory modules includes addressing, for a first half of a memory module, a read command to a first register address and performing read training using a first set of bit values received in response to addressing using the first register address. For a second half of the memory module, the same read command is used, but read training is performed using a second set of bit values received in response to addressing using the first register address.
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公开(公告)号：US20170344421A1
公开(公告)日：2017-11-30
申请号：US15168045
申请日：2016-05-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl
CPC classification number: G06F11/1068 , G06F3/0619 , G06F3/064 , G06F3/0673 , G11C29/42 , G11C29/4401 , G11C29/52 , G11C29/76 , G11C2029/0411
Abstract: A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ECC) bits. The first error counter counts errors in the returned data, and provides a control signal in response to reaching a predetermined state. The scrubber controls the memory channel controller to read data sequentially and periodically from a plurality of addresses of a memory system, and in response to detecting a correctable error, to rewrite corrected data. The data processor is responsive to the control signal to perform a post package repair operation with the memory system in response to the control signal.
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公开(公告)号：US09214199B2
公开(公告)日：2015-12-15
申请号：US14497977
申请日：2014-09-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl , Oswin E. Housty , Gerald Talbot
CPC classification number: G11C7/00 , G06F3/0614 , G06F3/0653 , G06F12/16 , G06F13/1689 , G11C11/40 , G11C29/021 , G11C29/028
Abstract: A method is provided for performing memory operations in response to instructions to perform a double data rate (DDR) memory reference voltage training in the voltage domain by a processing device and determining a DDR memory reference voltage and a DDR memory delay time based upon the memory operation. Computer readable storage media are also provided. A circuit is provided that includes a communication interface portion coupled to a memory and to a processing device. The circuit also includes a circuit portion, coupled to the communication interface portion that has a hardware state machine or an algorithm. The state machine or algorithm provides instructions to the processing device to perform a double data rate (DDR) reference voltage training in the voltage domain.
Abstract translation: 提供了一种用于响应于通过处理装置执行电压域中的双数据速率（DDR）存储器参考电压训练的指令执行存储器操作的方法，并且基于存储器确定DDR存储器参考电压和DDR存储器延迟时间 操作。 还提供计算机可读存储介质。 提供了一种电路，其包括耦合到存储器和处理设备的通信接口部分。 电路还包括耦合到具有硬件状态机或算法的通信接口部分的电路部分。 状态机或算法向处理设备提供指令以执行电压域中的双数据速率（DDR）参考电压训练。
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Patent Agency Ranking
公开(公告)号：US09141541B2
公开(公告)日：2015-09-22
申请号：US14032887
申请日：2013-09-20
Applicant: Advanced Micro Devices, Inc.
Inventor： Vydhyanathan Kalyanasundharam , Kevin M. Brandl , Adnan Dhanani
CPC classification number: G06F12/0607
Abstract: A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits.
Abstract translation: 一种用于将地址空间映射到非功率数量的存储器通道的系统和方法。 地址被转换并交错到存储器通道，使得每个存储器通道具有相等量的映射地址空间。 地址空间被划分成两个区域，并且第一翻译函数用于针对第一区域的存储器请求，并且第二翻译函数用于针对第二区域的存储器请求。 第一翻译函数基于第一组地址位，第二翻译函数基于第二组地址位。
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公开(公告)号：US20240403065A1
公开(公告)日：2024-12-05
申请号：US18680644
申请日：2024-05-31
Applicant: Advanced Micro Devices, Inc.
Inventor： Sriram Sambamurthy , Indrani Paul , Kevin M. Brandl , James R. Magro , Zhao Hui Yu , Oswin E. Housty
IPC: G06F9/4401
Abstract: The disclosed device includes multiple special purpose processors that are configured to perform, in parallel, a power on transition sequence for the device, which can involve restoring a data state of components of the device using data stored in local storages of the special purpose processors. Various other methods, systems, and computer-readable media are also disclosed.
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公开(公告)号：US12158827B2
公开(公告)日：2024-12-03
申请号：US18091163
申请日：2022-12-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Kedarnath Balakrishnan , Kevin M. Brandl , James R. Magro
Abstract: A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests, respectively, to the command queue. The arbiter uses the plurality of arbitration rules for both the read migration requests and the write migration requests, and the read access requests and the write access requests.
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公开(公告)号：US20240004560A1
公开(公告)日：2024-01-04
申请号：US17853393
申请日：2022-06-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Jean J. Chittilappilly , Kevin M. Brandl , Michael L. Choate
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0659 , G06F3/0673
Abstract: A data processor is adapted to couple to a memory. The data processor includes a memory operation array, a power engine, and an initialization circuit. The memory operation array includes a command portion and a data portion. The power engine has an input for receiving power state change request signals and an output for providing memory operations responsive to instructions stored in the command portion. The initialization circuit populates the data portion such that consecutive memory operations are separated by an amount corresponding to a predetermined minimum timing parameter.
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公开(公告)号：US11694739B2
公开(公告)日：2023-07-04
申请号：US17564575
申请日：2021-12-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Kevin M. Brandl , Kedarnath Balakrishnan , Jing Wang , Guanhao Shen
IPC: G11C11/406
CPC classification number: G11C11/40615
Abstract: A memory controller interfaces with a random access memory over a memory channel. A refresh control circuit monitors an activate counter which counts a rolling number of activate commands sent over the memory channel to a memory region of the memory. In response to the activate counter being above an intermediate management threshold value, the refresh control circuit only issue a refresh management (RFM) command if there is no REF command currently held at the refresh command circuit for the memory region.
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