公开(公告)号：US20060255423A1

公开(公告)日：2006-11-16

申请号：US11126816

申请日：2005-05-11

申请人： Sei-Hyung Ryu ,  Anant Agarwal

发明人： Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L29/15

CPC分类号： H01L29/6606 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/872

摘要： Integral structures that block the current conduction of the built-in PiN diode in a junction barrier Schottky (JBS) structure are provided. A Schottky diode may be incorporated in series with the PiN diode, where the Schottky diode is of opposite direction to that of the PiN diode. A series resistance or and insulating layer may be provided between the PiN diode and a Schottky contact. Silicon carbide Schottky diodes and methods of fabricating silicon carbide Schottky diodes that include a silicon carbide junction barrier region disposed within a drift region of the diode are also provided. The junction barrier region includes a first region of silicon carbide having a first doping concentration in the drift region of the diode and a second region of silicon carbide in the drift region and disposed between the first region of silicon carbide and a Schottky contact of the Schottky diode. The second region is in contact with the first region of silicon carbide and the Schottky contact. The second region of silicon carbide has a second doping concentration that is less than the first doping concentration.

摘要翻译： 提供阻塞内部PiN二极管在结屏障肖特基（JBS）结构中的电流传导的积分结构。 肖特基二极管可以与PiN二极管串联，其中肖特基二极管与PiN二极管的方向相反。 可以在PiN二极管和肖特基接触之间提供串联电阻或绝缘层。 还提供了碳化硅肖特基二极管和制造碳化硅肖特基二极管的方法，其包括设置在二极管的漂移区域内的碳化硅结壁垒区域。 结阻挡区域包括在二极管的漂移区域中具有第一掺杂浓度的碳化硅的第一区域和漂移区域中的第二碳化硅区域，并且设置在碳化硅的第一区域与肖特基的肖特基接触之间 二极管。 第二区域与碳化硅的第一区域和肖特基接触部接触。 碳化硅的第二区域具有小于第一掺杂浓度的第二掺杂浓度。

公开(公告)号：US06770911B2

公开(公告)日：2004-08-03

申请号：US09952064

申请日：2001-09-12

申请人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

发明人： Anant Agarwal ,  Sei-Hyung Ryu ,  John W. Palmour

IPC分类号： H01L29417

CPC分类号： H01L31/1113 ,  Y10S438/931

摘要： Large area silicon carbide devices, such as light-activated silicon carbide thyristors, having only two terminals are provided. The silicon carbide devices are selectively connected in parallel by a connecting plate. Silicon carbide thyristors are also provided having a portion of the gate region of the silicon carbide thyristors exposed so as to allow light of an energy greater than about 3.25 eV to activate the gate of the thyristor. The silicon carbide thyristors may be symmetric or asymmetrical. A plurality of the silicon carbide thyristors may be formed on a wafer, a portion of a wafer or multiple wafers. Bad cells may be determined and the good cells selectively connected by a connecting plate.

摘要翻译： 提供仅具有两个端子的大面积碳化硅器件，例如光激活碳化硅晶闸管。 碳化硅器件通过连接板选择性地并联连接。 还提供了碳化硅晶闸管，其具有暴露的碳化硅晶闸管的栅极区域的一部分，以允许大于约3.25eV的能量的光来激活晶闸管的栅极。 碳化硅晶闸管可以是对称的或不对称的。 多个碳化硅晶闸管可以形成在晶片，晶片的一部分或多个晶片上。 可以确定坏细胞，并且通过连接板选择性地连接良好的细胞。

公开(公告)号：US09396946B2

公开(公告)日：2016-07-19

申请号：US13229266

申请日：2011-09-09

申请人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Erik Maki ,  Jason Gurganus ,  Daniel Jenner Lichtenwalner

发明人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Erik Maki ,  Jason Gurganus ,  Daniel Jenner Lichtenwalner

IPC分类号： H01L21/3205 ,  H01L21/04 ,  H01L21/02 ,  H01L29/51 ,  H01L29/739 ,  H01L29/78 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

摘要： Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

摘要翻译： 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：US09269580B2

公开(公告)日：2016-02-23

申请号：US13229276

申请日：2011-09-09

申请人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

发明人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

IPC分类号： H01L29/51 ,  H01L29/78 ,  H01L21/28 ,  H01L21/04 ,  H01L21/02 ,  H01L29/739 ,  H01L29/06 ,  H01L29/16

CPC分类号： H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

摘要： Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

摘要翻译： 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：US08680587B2

公开(公告)日：2014-03-25

申请号：US13229749

申请日：2011-09-11

申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/66

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/8611 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.

摘要翻译： 本公开总体上涉及具有衬底，设置在衬底上的漂移层和设置在漂移层的有源区上的肖特基层的肖特基二极管。 选择用于肖特基金属的金属和用于漂移层的半导体材料以在漂移层和肖特基层之间提供低势垒高度的肖特基结。

公开(公告)号：US08664665B2

公开(公告)日：2014-03-04

申请号：US13229752

申请日：2011-09-11

申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

IPC分类号： H01L29/15

CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66143 ,  H01L2224/02166 ,  H01L2924/13055 ,  H01L2924/00

摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.

摘要翻译： 本发明一般涉及一种肖特基二极管，其具有衬底，设置在衬底上的漂移层以及设置在衬底的有源区上的肖特基层。 在位于肖特基层正下方的漂移层中提供了结屏障阵列。 结势垒阵列的元件通常是漂移层中的掺杂区域。 为了增加这些掺杂区域的深度，可以在要形成结屏障阵列的元件的漂移层的表面中形成单独的凹槽。 一旦凹陷形成在漂移层中，则凹部周围和底部的区域被掺杂以形成连接屏障阵列的相应元件。

公开(公告)号：US20120326163A1

公开(公告)日：2012-12-27

申请号：US13229276

申请日：2011-09-09

申请人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

发明人： Sarit Dhar ,  Lin Cheng ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Jason Gurganus

IPC分类号： H01L29/161 ,  H01L29/49 ,  H01L21/28

CPC分类号： H01L29/7802 ,  H01L21/02142 ,  H01L21/02164 ,  H01L21/02172 ,  H01L21/02175 ,  H01L21/022 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/02378 ,  H01L21/045 ,  H01L21/049 ,  H01L29/0619 ,  H01L29/1606 ,  H01L29/1608 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7395 ,  H01L29/78 ,  H01L29/7813

摘要： Embodiments of a semiconductor device having increased channel mobility and methods of manufacturing thereof are disclosed. In one embodiment, the semiconductor device includes a substrate including a channel region and a gate stack on the substrate over the channel region. The gate stack includes an alkaline earth metal. In one embodiment, the alkaline earth metal is Barium (Ba). In another embodiment, the alkaline earth metal is Strontium (Sr). The alkaline earth metal results in a substantial improvement of the channel mobility of the semiconductor device.

摘要翻译： 公开了具有增加的信道移动性的半导体器件及其制造方法的实施例。 在一个实施例中，半导体器件包括在沟道区上的衬底上包括沟道区和栅叠层的衬底。 栅极堆叠包括碱土金属。 在一个实施方案中，碱土金属是钡（Ba）。 在另一个实施方案中，碱土金属是锶（Sr）。 碱土金属导致半导体器件的沟道迁移率的显着改善。

公开(公告)号：US20120280252A1

公开(公告)日：2012-11-08

申请号：US13102510

申请日：2011-05-06

申请人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

发明人： Sei-Hyung Ryu ,  Doyle Craig Capell ,  Lin Cheng ,  Sarit Dhar ,  Charlotte Jonas ,  Anant Agarwal ,  John Palmour

IPC分类号： H01L29/12 ,  H01L29/06 ,  H01L29/772

CPC分类号： H01L29/7802 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/7395

摘要： A semiconductor device includes a drift layer having a first conductivity type, a well region in the drift layer having a second conductivity type opposite the first conductivity type, and a source region in the well region, The source region has the first conductivity type and defines a channel region in the well region. The source region includes a lateral source region adjacent the channel region and a plurality of source contact regions extending away from the lateral source region opposite the channel region. A body contact region having the second conductivity type is between at least two of the plurality of source contact regions and is in contact with the well region. A source ohmic contact overlaps at least one of the source contact regions and the body contact region. A minimum dimension of a source contact area of the semiconductor device is defined by an area of overlap between the source ohmic contact and the at least one source contact region.

公开(公告)号：US20100090271A1

公开(公告)日：2010-04-15

申请号：US12560729

申请日：2009-09-16

申请人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

发明人： Allen Hefner ,  Sei-Hyung Ryu ,  Anant Agarwal

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7803 ,  H01L21/0465 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7828 ,  H01L29/861

摘要： A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse biase the p-n junction between the drift region and the body region.

摘要翻译： 半导体器件包括具有第一导电类型的漂移层和与漂移层相邻的体区。 身体区域具有与第一导电类型相反的第二导电类型，并与漂移层形成p-n结。 该器件还包括在体区中具有第一导电类型的接触器区域和从接触器区域延伸穿过体区的分流通道区域到漂移层。 分流通道区域具有第一导电类型。 该装置还包括与主体区域和接触器区域电接触的第一端子和与漂移层电接触的第二端子。 分流沟道区域具有选择的长度，厚度和掺杂浓度，使得：1）当跨越第一和第二端子施加零电压时，并联沟道区域完全耗尽，2）并联沟道在小于 内置电位漂移层到体区pn结，和/或3）并联通道对于反向偏置漂移区和体区之间的pn结的电压不导通。

公开(公告)号：US09337268B2

公开(公告)日：2016-05-10

申请号：US13108366

申请日：2011-05-16

申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。