公开(公告)号：US20200350178A1

公开(公告)日：2020-11-05

申请号：US16901210

申请日：2020-06-15

申请人： Applied Materials, Inc.

发明人： He Ren ,  Jong Mun Kim ,  Maximillian Clemons ,  Minrui Yu ,  Mehul Naik ,  Chentsau Ying

IPC分类号： H01L21/3213

摘要： Exemplary methods of etching semiconductor substrates may include flowing a halogen-containing precursor into a processing region of a semiconductor processing chamber. The processing region may house a substrate having a conductive material and an overlying mask material. The conductive material may be characterized by a first surface in contact with the mask material, and the mask material may define an edge region of the conductive material. The methods may include contacting the edge region of the conductive material with the halogen-containing precursor and the oxygen-containing precursor. The methods may include etching in a first etching operation the edge region of the conductive material to a partial depth through the conductive material to produce a footing of conductive material protruding along the edge region of the conductive material. The methods may also include removing the footing of conductive material in a second etching operation.

公开(公告)号：US10109520B2

公开(公告)日：2018-10-23

申请号：US15285011

申请日：2016-10-04

申请人： APPLIED MATERIALS, INC.

发明人： Sree Rangasai V. Kesapragada ,  Kevin Moraes ,  Srinivas Guggilla ,  He Ren ,  Mehul Naik ,  David Thompson ,  Weifeng Ye ,  Yana Cheng ,  Yong Cao ,  Xianmin Tang ,  Paul F. Ma ,  Deenesh Padhi

IPC分类号： H01L21/768 ,  H01L21/02

摘要： In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.

公开(公告)号：US09847289B2

公开(公告)日：2017-12-19

申请号：US14291466

申请日：2014-05-30

申请人： Applied Materials, Inc.

发明人： Mehul Naik ,  Paul F. Ma ,  Srinivas D. Nemani

IPC分类号： H01L21/02 ,  H01L21/3065 ,  H01L23/522 ,  H01L23/528 ,  H01L21/306 ,  H01L21/768 ,  H01L23/532 ,  H01J37/32

CPC分类号： H01L23/5226 ,  H01J37/32091 ,  H01L21/02068 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary methods of forming a semiconductor structure may include etching a via through a semiconductor structure to expose a first circuit layer interconnect metal. The methods may include forming a layer of a material overlying the exposed first circuit layer interconnect metal. The methods may also include forming a barrier layer within the via having minimal coverage along the bottom of the via. The methods may additionally include forming a second circuit layer interconnect metal overlying the layer of material.

公开(公告)号：US09847252B2

公开(公告)日：2017-12-19

申请号：US15453675

申请日：2017-03-08

申请人： APPLIED MATERIALS, INC.

发明人： Bencherki Mebarki ,  Srinivas D. Nemani ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

CPC分类号： H01L21/76897 ,  H01L21/76834 ,  H01L21/76883

摘要： A method of processing a substrate includes: depositing an etch stop layer atop a first dielectric layer; forming a feature in the etch stop layer and the first dielectric layer; depositing a first metal layer to fill the feature; etching the first metal layer to form a recess; depositing a second dielectric layer to fill the recess wherein the second dielectric layer is a low-k material suitable as a metal and oxygen diffusion barrier; forming a patterned mask layer atop the substrate to expose a portion of the second dielectric layer and the etch stop layer; etching the exposed portion of the second dielectric layer to a top surface of the first metal layer to form a via in the second dielectric layer; and depositing a second metal layer atop the substrate, wherein the second metal layer is connected to the first metal layer by the via.

公开(公告)号：US09761489B2

公开(公告)日：2017-09-12

申请号：US13987667

申请日：2013-08-20

申请人： Applied Materials, Inc.

发明人： Bencherki Mebarki ,  Huixiong Dai ,  Yongmei Chen ,  He Ren ,  Mehul Naik

IPC分类号： H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC分类号： H01L21/76897 ,  H01L21/32139 ,  H01L21/76885 ,  H01L23/53257 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where the conductive contacts of the interconnect structure are fabricated using solely subtractive techniques applied to conformal layers of conductive materials.

公开(公告)号：US09711397B1

公开(公告)日：2017-07-18

申请号：US15140955

申请日：2016-04-28

申请人： APPLIED MATERIALS, INC.

发明人： Nikolaos Bekiaris ,  Mehul Naik ,  Zhiyuan Wu

IPC分类号： H01L21/768 ,  H01L21/285

CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76883 ,  H01L23/53209

摘要： Resistance increase in Cobalt interconnects due to nitridation occurring during removal of surface oxide from Cobalt interconnects and deposition of Nitrogen-containing film on Cobalt interconnects is solved by a Hydrogen thermal anneal or plasma treatment. Removal of the Nitrogen is through a thin overlying layer which may be a dielectric barrier layer or an etch stop layer.

公开(公告)号：US09257330B2

公开(公告)日：2016-02-09

申请号：US14483578

申请日：2014-09-11

申请人： Applied Materials, Inc.

发明人： Amit Chatterjee ,  Geetika Bajaj ,  Pramit Manna ,  He Ren ,  Tapash Chakraborty ,  Srinivas D. Nemani ,  Mehul Naik ,  Robert Jan visser ,  Abhijit Basu Mallick

IPC分类号： H01L21/68 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L21/76835 ,  H01L21/76838 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.

摘要翻译： 描述了在半导体电路的金属互连上沉积有效扩散阻挡层的薄的低介电常数层的方法。 每个具有头部和尾部的分子的自组装单层（SAM）沉积在金属上。 SAM分子自对准，其中头部部分被配制成选择性地键合到金属层，离开设置在分子远端的尾部。 随后在SAM上沉积介电层，化学键合到SAM分子的尾部。

公开(公告)号：US20150348902A1

公开(公告)日：2015-12-03

申请号：US14291466

申请日：2014-05-30

申请人： Applied Materials, Inc.

发明人： Mehul Naik ,  Paul F. Ma ,  Srinivas D. Nemani

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01J37/32091 ,  H01L21/02068 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/76807 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Exemplary methods of forming a semiconductor structure may include etching a via through a semiconductor structure to expose a first circuit layer interconnect metal. The methods may include forming a layer of a material overlying the exposed first circuit layer interconnect metal. The methods may also include forming a barrier layer within the via having minimal coverage along the bottom of the via. The methods may additionally include forming a second circuit layer interconnect metal overlying the layer of material.

摘要翻译： 形成半导体结构的示例性方法可以包括通过半导体结构蚀刻通孔以暴露第一电路层互连金属。 所述方法可以包括形成覆盖暴露的第一电路层互连金属的材料层。 所述方法还可以包括在通孔内沿着通孔底部形成具有最小覆盖范围的阻挡层。 所述方法还可以包括形成覆盖在所述材料层上的第二电路层互连金属。

公开(公告)号：US20240321641A1

公开(公告)日：2024-09-26

申请号：US18606739

申请日：2024-03-15

申请人： Applied Materials, Inc.

发明人： Hao Jiang ,  Jong Mun Kim ,  Jonathan Qian ,  He Ren ,  Mehul Naik

IPC分类号： H01L21/822 ,  H01L21/311

CPC分类号： H01L21/8221 ,  H01L21/31116

摘要： A method includes forming a planarization layer to a position below an upper transistor device region of a base structure of an electronic device and above a lower transistor device region of the base structure. The base structure includes a plurality of features. The method further includes forming spacer material along the base structure and the planarization layer, modifying the spacer material formed along bottom trenches of the base structure to obtain modified spacer material, and forming a spacer layer by using a wet etch process to remove the modified spacer material. Modifying the spacer material formed along the bottom trenches of the base structure to obtain the modified spacer material includes performing a dry etch process targeting the spacer material formed along the bottom trenches of the base structure.

公开(公告)号：US12046508B2

公开(公告)日：2024-07-23

申请号：US18108338

申请日：2023-02-10

申请人： APPLIED MATERIALS, INC.

发明人： Shi You ,  He Ren ,  Naomi Yoshida ,  Nikolaos Bekiaris ,  Mehul Naik ,  Martin Jay Seamons ,  Jingmei Liang ,  Mei-Yee Shek

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/67

CPC分类号： H01L21/76837 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/67103 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/02326

摘要： Embodiments herein provide for oxygen based treatment of low-k dielectric layers deposited using a flowable chemical vapor deposition (FCVD) process. Oxygen based treatment of the FCVD deposited low-k dielectric layers desirably increases the Ebd to capacitance and reliability of the devices while removing voids. Embodiments include methods and apparatus for making a semiconductor device including: etching a metal layer disposed atop a substrate to form one or more metal lines having a top surface, a first side, and a second side; depositing a passivation layer atop the top surface, the first side, and the second side under conditions sufficient to reduce or eliminate oxygen contact with the one or more metal lines; depositing a flowable layer of low-k dielectric material atop the passivation layer in a thickness sufficient to cover the one or more metal lines; and contacting the flowable layer of low-k dielectric material with oxygen under conditions sufficient to anneal and increase a density of the low-k dielectric material.