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    Structure for relaxed SiGe buffers including method and apparatus for forming
    32.
    发明授权
    Structure for relaxed SiGe buffers including method and apparatus for forming 有权

    公开(公告)号：US09752224B2

    公开(公告)日：2017-09-05

    申请号：US15210030

    申请日：2016-07-14

    Applicant: Applied Materials, Inc.

    Inventor： Zhiyuan Ye ,  Errol Antonio C. Sanchez ,  Keun-Yong Ban ,  Xinyu Bao

    IPC: H01L21/02 ,  C23C8/02

    CPC classification number: C23C8/02 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/0262

    Abstract: Embodiments of the present disclosures provide methods and apparatus for manufacturing semiconductor devices such as transistors used for amplifying or switching electronic signals. Specifically, embodiments of the present disclosure generally relate to a semiconductor device having a film stack including an interlayer of semiconductor material and a buffer layer of semiconductor material underneath an active device layer. In various embodiments, the interlayer may include group III-V semiconductor materials formed between a first surface of a silicon-based substrate and the buffer layer. In certain embodiments the buffer layer may comprise group IV semiconductor materials. The interlayer may have a lattice constant designed to mitigate lattice mismatch between the group IV buffer layer and the silicon-based substrate. The buffer layer may provide improved integration of the active device layer to improve the performance of the resulting device.

    Arsenic diffusion profile engineering for transistors
    33.
    发明授权
    Arsenic diffusion profile engineering for transistors 有权

    公开(公告)号：US12249626B2

    公开(公告)日：2025-03-11

    申请号：US17628634

    申请日：2020-07-01

    Applicant: Applied Materials, Inc.

    Inventor： Patricia M. Liu ,  Flora Fong-Song Chang ,  Zhiyuan Ye

    IPC: H01L21/00 ,  H01L21/02 ,  H01L21/22 ,  H01L29/167 ,  H01L29/66 ,  H01L29/78

    Abstract: Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.

    Methods and assemblies for gas flow ratio control
    36.
    发明授权
    Methods and assemblies for gas flow ratio control 有权

    公开(公告)号：US11923221B2

    公开(公告)日：2024-03-05

    申请号：US17935810

    申请日：2022-09-27

    Applicant: Applied Materials, Inc.

    Inventor： Kevin Brashear ,  Ashley M. Okada ,  Dennis L. Demars ,  Zhiyuan Ye ,  Jaidev Rajaram ,  Marcel E. Josephson

    IPC: C23C16/455 ,  G05D11/13 ,  H01L21/67

    CPC classification number: H01L21/67253 ,  G05D11/132 ,  H01L21/67017

    Abstract: A master controller determines a first flow setpoint for a process flow gas and/or a carrier gas flow through a first mass flow controller. The master controller obtains a back pressure setpoint of a distribution manifold and determines a second flow setpoint for the process gas flow and/or the carrier gas flow through a second mass flow controller or a back pressure controller based on the determined first flow setpoint and the obtained back pressure setpoint. The master controller controls the process gas flow and/or the carrier gas flow through the first mass flow controller to the first flow setpoint and the second mass flow controller and/or the back pressure controller to the second flow setpoint. The master controller controls the back pressure of the distribution manifold to the back pressure set point in view of a back pressure reading from a back pressure sensor of the distribution manifold.

    Transistor and method for forming a transistor
    39.
    发明授权
    Transistor and method for forming a transistor 有权

    公开(公告)号：US11195914B2

    公开(公告)日：2021-12-07

    申请号：US16588901

    申请日：2019-09-30

    Applicant: Applied Materials, Inc.

    Inventor： Patricia M. Liu ,  Flora Fong-Song Chang ,  Zhiyuan Ye

    IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/24

    Abstract: Embodiments of the present disclosure relate to a transistor and methods for forming a transistor. A transistor includes a gate electrode structure disposed over a channel region, a source/drain extension region disposed adjacent to the channel region, and a source/drain region disposed on the source/drain extension region. The source/drain region includes antimony (Sb). The method of forming a transistor includes forming the source/drain extension region and forming the source/drain region on the source/drain extension region. The antimony helps prevent unwanted migration of dopants from the source/drain region to the source/drain extension region.

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