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31.发明授权Symmetrical program and erase scheme to improve erase time degradation in NAND devices 有权对称编程和擦除方案，以改善NAND器件中的擦除时间退化公开(公告)号：US06246610B1
公开(公告)日：2001-06-12
申请号：US09511652
申请日：2000-02-22
IPC分类号： G11C1604
摘要： A programming and erase method that extends erase time degradation of nonvolatile memory devices by using a constant erase voltage and a set of program voltages, where the average program voltage of the set of the program voltages is approximately equal to the constant erase voltage.
摘要翻译： 一种编程和擦除方法，其通过使用恒定擦除电压和一组编程电压来延长非易失性存储器件的擦除时间劣化，其中编程电压组的平均编程电压近似等于恒定擦除电压。
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32.发明授权
公开(公告)号：US6159795A
公开(公告)日：2000-12-12
申请号：US109664
申请日：1998-07-02
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11546 , Y10S438/976
摘要： An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.
摘要翻译： 执行中间植入步骤以优化浮动型存储器集成电路的周边部分中的晶体管的性能。 在相应的浮动栅型存储器件中形成浮置栅极的多晶硅层（Poly 1）防止优化注入穿透到形成浮栅存储器件的芯区域中。 这允许在不需要附加掩模的情况下执行优化植入，从而降低成本和生产时间。
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33.发明授权Barrier layer decreases nitrogen contamination of peripheral gate regions during tunnel oxide nitridation 有权阻挡层在隧道氧化物氮化期间减少外围栅极区域的氮污染
公开(公告)号：US6143608A
公开(公告)日：2000-11-07
申请号：US283308
申请日：1999-03-31
申请人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
发明人： Yue-Song He , Masaaki Higashitani , Hao Fang , Narbeh Derhacobian , Bill Cox , Kent Chang , Kelwin Ko , Maria Chow-Chan
IPC分类号： H01L21/8247 , H01L27/105 , H01L21/336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11536
摘要： This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.
摘要翻译： 本发明描述了在半导体芯片的周边区域中制造栅极氧化物区域的方法，其中栅极氧化物区域具有改善的电性能。 所述方法包括在半导体芯片的周边上沉积阻挡层，以防止在半导体芯片的芯区域中的氮化步骤期间将杂质氮原子引入周围。 通过防止周围的栅极区域的污染，如此产生的栅极氧化物区域具有增加的击穿电压和增加的可靠性。 本发明描述了用于蚀刻用于保护周边免受隧道氧化物氮化的阻挡层的方法。 用本发明的方法制造的半导体器件具有更长的预期寿命，并且可以以较高的器件密度制造。
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34.发明授权Read operations and circuits for memory devices having programmable elements, including programmable resistance elements 有权读取具有可编程元件的存储器件的操作和电路，包括可编程电阻元件公开(公告)号：US09570166B1
公开(公告)日：2017-02-14
申请号：US14572646
申请日：2014-12-16
CPC分类号： G11C13/004 , G11C7/06 , G11C11/56 , G11C11/5614 , G11C13/0002 , G11C13/0011 , G11C16/26 , G11C2013/0054 , G11C2013/0057
摘要： A memory devices and methods can use multiple sense operations to detect a state of memory elements in a marginal state. In some embodiments, an evaluation circuit can generates an output value for a memory element in response multiple sense results for the same memory element.
摘要翻译： 存储器件和方法可以使用多重检测操作来检测处于边缘状态的存储器元件的状态。 在一些实施例中，评估电路可以响应于相同存储器元件的多个感测结果而产生用于存储器元件的输出值。
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公开(公告)号：US08183551B2
公开(公告)日：2012-05-22
申请号：US11267788
申请日：2005-11-03
IPC分类号： H01L45/00
CPC分类号： H01L45/1226 , G11C13/0004 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/1683 , H03K19/02
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。
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公开(公告)号：US20070235707A1
公开(公告)日：2007-10-11
申请号：US11811077
申请日：2007-06-07
IPC分类号： H01L45/00
CPC分类号： H01L45/1226 , G11C13/0004 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/1683 , H03K19/02
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
摘要翻译： 相变装置，特别是多端子相变装置，包括通过相变材料桥接在一起的第一和第二有源端子，其中导电性可以根据施加到控制电极的控制信号进行修改。 这种结构允许在两个有效端子之间可以产生电连接的应用，连接的控制使用单独的终端或终端实现。 因此，可以独立于两个有源端子之间的路径的电阻来增加加热器元件的电阻。 这允许使用较小的加热器元件，因此需要较少的电流以在每单位面积上产生相同量的焦耳加热。 加热元件的电阻不影响相变装置的总电阻。 编程控制可以通过相变装置放置在主信号路径之外，减少相关电容和器件电阻的影响。
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公开(公告)号：US20070096071A1
公开(公告)日：2007-05-03
申请号：US11267788
申请日：2005-11-03
IPC分类号： H01L29/02
CPC分类号： H01L45/1226 , G11C13/0004 , H01L45/06 , H01L45/1206 , H01L45/122 , H01L45/126 , H01L45/1683 , H03K19/02
摘要： Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device. The programming control can be placed outside of the main signal path through the phase change device, reducing the impact of the associated capacitance and resistance of the device.
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公开(公告)号：US07095076B1
公开(公告)日：2006-08-22
申请号：US10897185
申请日：2004-07-21
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0408 , H01L27/115 , H01L27/11558
摘要： A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.
摘要翻译： 一种方法，装置和系统，其中嵌入式存储器包括一个或多个包括耦合电容器，读取晶体管和隧道电容器的可电气可变的非易失性存储器单元。 耦合电容器具有由N +掺杂材料和P +掺杂材料构成的第一栅极和与N +掺杂区域邻接的P +掺杂区域。 邻接N +掺杂区域的P +掺杂区围绕第一栅极。 读取晶体管具有第二栅极。 隧道电容器具有由N +掺杂材料和P +掺杂材料构成的第三栅极。
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公开(公告)号：US06788574B1
公开(公告)日：2004-09-07
申请号：US10295742
申请日：2002-11-15
IPC分类号： G11C1400
CPC分类号： H01L27/11521 , G11C16/0408 , H01L27/115 , H01L27/11558
摘要： A method, apparatus, and system in which an embedded memory comprises one or more electrically-alterable non-volatile memory cells that include a coupling capacitor, a read transistor, and a tunneling capacitor. The coupling capacitor has a first gate composed of both N+ doped material and P+ doped material, and a P+ doped region abutted to a N+ doped region. The P+ doped region abutted to the N+ doped region surrounds the first gate. The read transistor has a second gate. The tunneling capacitor has a third gate composed of both N+ doped material and P+ doped material.
摘要翻译： 一种方法，装置和系统，其中嵌入式存储器包括一个或多个包括耦合电容器，读取晶体管和隧道电容器的可电气可变的非易失性存储器单元。 耦合电容器具有由N +掺杂材料和P +掺杂材料构成的第一栅极和与N +掺杂区域邻接的P +掺杂区域。 邻接N +掺杂区域的P +掺杂区围绕第一栅极。 读取晶体管具有第二栅极。 隧道电容器具有由N +掺杂材料和P +掺杂材料构成的第三栅极。
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公开(公告)号：US06590811B1
公开(公告)日：2003-07-08
申请号：US10173262
申请日：2002-06-17
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C11/5671 , G11C16/04 , G11C16/0475 , G11C16/10 , G11C16/3404 , G11C16/3436 , G11C16/3445 , G11C16/3459 , G11C29/50 , G11C29/50004
摘要： A method and system for programming of the normal bits of a memory array of dual bit memory cells is accomplished by programming at a substantially high delta VT. The substantially higher VT assures that the memory array will maintain programmed data and erase data consistently after higher temperature stresses and/or customer operation over substantial periods of time. Furthermore, by utilizing substantially high gate and drain voltages during programming, programming times are kept short without degrading charge loss. A methodology is provided that determines the charge loss for single bit operation during program and erase cycles. The charge losses over cycling and stress are then utilized to determine an appropriate delta VT to be programmed into a command logic and state machine.
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