Electrochemical Fabrication Method Including Elastic Joining of Structures
    31.
    发明申请
    Electrochemical Fabrication Method Including Elastic Joining of Structures 有权
    包括结构弹性连接的电化学制造方法

    公开(公告)号:US20120137497A1

    公开(公告)日:2012-06-07

    申请号:US13287437

    申请日:2011-11-02

    IPC分类号: B23P25/00

    摘要: Embodiments are directed to methods for forming multi-layer three-dimensional structures involving the joining of at least two structural elements, at least one of which is formed as a multi-layer three-dimensional structure, wherein the joining occurs via one of: (1) elastic deformation and elastic recovery and subsequent retention of elements relative to each other, (2) relative deformation of an initial portion of at least one element relative to another portion of the at least one element until the at least two elements are in a desired retention position after which the deformation is reduced or eliminated and a portion of at least one element is brought into position which in turn locks the at least two elements together via contact with one another including contact with the initial portion of at least one element, or (3) moving a retention region of one element into the retention region of the other element, without deformation of either element, along a path including a loading region of the other element and wherein during normal use the first and second elements are configured relative to one another so that the loading region of the second elements is not accessible to the retention region of the first element.

    摘要翻译: 实施例涉及用于形成多层三维结构的方法,所述多层三维结构涉及至少两个结构元件的接合,其中至少一个结构元件形成为多层三维结构,其中通过以下之一进行接合:( 1)弹性变形和弹性恢复以及随后元件相对于彼此的保持,(2)至少一个元件的初始部分相对于至少一个元件的另一部分的相对变形,直到至少两个元件处于 期望的保持位置,在此之后,变形被减小或消除,并且至少一个元件的一部分进入位置,其又通过彼此接触将至少两个元件锁定在一起,包括与至少一个元件的初始部分的接触, 或(3)将一个元件的保持区域移动到另一个元件的保持区域中,而不会使任一元件变形,沿着包括装载物 g区域,并且其中在正常使用期间,第一和第二元件相对于彼此构造,使得第二元件的加载区域不能被第一元件的保持区域访问。

    Multi-Layer Three-Dimensional Structures Having Features Smaller Than a Minimum Feature Size Associated With the Formation of Individual Layers
    34.
    发明申请
    Multi-Layer Three-Dimensional Structures Having Features Smaller Than a Minimum Feature Size Associated With the Formation of Individual Layers 审中-公开
    具有小于单个层的形成的最小特征尺寸的特征的多层三维结构

    公开(公告)号:US20110198281A1

    公开(公告)日:2011-08-18

    申请号:US13040500

    申请日:2011-03-04

    IPC分类号: B01D39/00 C25D1/08 B32B5/18

    摘要: Embodiments of multi-layer three-dimensional structures and formation methods provide structures with effective feature (e.g. opening) sizes (e.g. virtual gaps) that are smaller than a minimum feature size (MFS) that exists on each layer as a result of the formation method used in forming the structures. In some embodiments, multi-layer structures include a first element (e.g. first patterned layer with a gap) and a second element (e.g. second patterned layer with a gap) positioned adjacent the first element to define a third element (e.g. a net gap or opening resulting from the combined gaps of the first and second elements) where the first and second elements have features that are sized at least as large as the minimum feature size and the third element, at least in part, has dimensions or defines dimensions smaller than the minimum feature size.

    摘要翻译: 多层三维结构和形成方法的实施例提供结构,其具有小于作为形成方法的结果存在于每个层上的最小特征尺寸(MFS)的有效特征(例如开口)尺寸(例如,虚拟间隙) 用于形成结构。 在一些实施例中,多层结构包括第一元件(例如具有间隙的第一图案化层)和邻近第一元件定位的第二元件(例如具有间隙的第二图案化层),以限定第三元件(例如,净间隙或 第一和第二元件的组合间隙产生的开口),其中第一和第二元件具有尺寸至少与最小特征尺寸一样大的特征,并且第三元件至少部分具有尺寸或尺寸小于 最小特征尺寸。

    Methods of and Apparatus for Electrochemically Fabricating Structures Via Interlaced Layers or Via Selective Etching and Filling of Voids
    36.
    发明申请
    Methods of and Apparatus for Electrochemically Fabricating Structures Via Interlaced Layers or Via Selective Etching and Filling of Voids 审中-公开
    电泳化学结构通过交错层或通过选择性蚀刻和填充空隙的方法和装置

    公开(公告)号:US20110022207A1

    公开(公告)日:2011-01-27

    申请号:US12851811

    申请日:2010-08-06

    申请人: Dennis R. Smalley

    发明人: Dennis R. Smalley

    摘要: Multi-layer structures are electrochemically fabricated by depositing a first material, selectively etching the first material (e.g. via a mask), depositing a second material to fill in the voids created by the etching, and then planarizing the depositions so as to bound the layer being created and thereafter adding additional layers to previously formed layers. The first and second depositions may be of the blanket or selective type. The repetition of the formation process for forming successive layers may be repeated with or without variations (e.g. variations in: patterns; numbers or existence of or parameters associated with depositions, etchings, and or planarization operations; the order of operations, or the materials deposited). Other embodiments form multi-layer structures using operations that interlace material deposited in association with some layers with material deposited in association with other layers.

    摘要翻译: 通过沉积第一材料,选择性地蚀刻第一材料(例如经由掩模),沉积第二材料以填充由蚀刻产生的空隙,然后平坦化沉积物以便结合层,电化学地制造多层结构 被创建并且之后向之前形成的层添加附加层。 第一和第二沉积可以是毯子或选择类型。 用于形成连续层的形成过程的重复可以在有或没有变化(例如:在图案上的变化;与沉积,蚀刻和/或平面化操作相关联的数量或存在或参数的变化)中重复,操作顺序或沉积的材料 )。 其他实施例使用使用与其它层相关联地沉积的材料与一些层相关联地沉积材料的操作形成多层结构。

    Methods of Reducing Interlayer Discontinuities in Electrochemically Fabricated Three-Dimensional Structures
    37.
    发明申请
    Methods of Reducing Interlayer Discontinuities in Electrochemically Fabricated Three-Dimensional Structures 审中-公开
    减少电化学三维结构中层间不连续性的方法

    公开(公告)号:US20100314257A1

    公开(公告)日:2010-12-16

    申请号:US12828283

    申请日:2010-06-30

    IPC分类号: C25D5/02

    摘要: Disclosed methods reduce the discontinuities that between individual layers of a structure that is formed at least in part using electrochemical fabrication techniques. Discontinuities may exist between layers of a structure as a result of up-facing or down-facing regions defined in data descriptive of the structure or they may exist as a result of building limitations, e.g., those that result in non-parallel orientation between a building axis and sidewall surfaces of layers. Methods for reducing discontinuities may be applied to all regions or only to selected regions of the structure. Methods may be tailored to improve the accuracy between an original design of the structure and the structure as fabricated or they may simply be used to smooth the discontinuities between layers. Methods may include deposition operations that selectively favor filling of the discontinuities and/or etching operations that selectively favor removal of material from protrusions that define discontinuities.

    摘要翻译: 公开的方法减少了使用电化学制造技术至少部分形成的结构的各个层之间的不连续性。 结构的层之间可能存在不连续性,这是由于在描述结构的数据中定义的面向上或向下的区域的结果,或者它们可能由于构建限制而存在,例如导致在 建筑轴线和层的侧壁表面。 用于减少不连续性的方法可以应用于所有区域或仅应用于结构的选定区域。 可以调整方法以提高结构的原始设计和所制造的结构之间的精度,或者可以简单地用于平滑层之间的不连续性。 方法可以包括选择性地有利于填充不连续性和/或蚀刻操作的沉积操作,其选择性地有利于从限定不连续性的突起中去除材料。

    Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings
    40.
    发明申请
    Method of Forming Electrically Isolated Structures Using Thin Dielectric Coatings 审中-公开
    使用薄介电涂层形成电隔离结构的方法

    公开(公告)号:US20100051466A1

    公开(公告)日:2010-03-04

    申请号:US12506547

    申请日:2009-07-21

    IPC分类号: C25D1/20 C25D5/10

    摘要: Electrochemical fabrication processes and apparatus for producing multi-layer structures where each layer includes the deposition of at least two materials and wherein the formation of at least some layers including operations for providing coatings of dielectric material that isolate at least portions of a first conductive material from (1) other portions of the first conductive material, (2) a second conductive material, or (3) another dielectric material, and wherein the thickness of the dielectric coatings are thin compared to the thicknesses of the layers used in forming the structures. In some preferred embodiments, portions of each individual layer are encapsulated by dielectric material while in other embodiments only boundaries between distinct regions of materials are isolated from one another by dielectric barriers.

    摘要翻译: 用于生产多层结构的电化学制造方法和装置,其中每个层包括至少两种材料的沉积,并且其中形成至少一些层,包括用于提供将第一导电材料的至少一部分与 (1)第一导电材料的其它部分,(2)第二导电材料或(3)另一种电介质材料,并且其中电介质涂层的厚度与用于形成结构的层的厚度相比较薄。 在一些优选实施例中,每个单独层的部分被电介质材料包封,而在其它实施例中,材料的不同区域之间的边界通过电介质屏障彼此隔离。