公开(公告)号：US5741740A

公开(公告)日：1998-04-21

申请号：US873836

申请日：1997-06-12

申请人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Ying-Ho Chen ,  Chen-Hua Yu

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/31612 ,  H01L21/76224 ,  Y10S148/05

摘要： A method for filling a trench within a silicon substrate. There is first provided a silicon substrate having a trench formed therein. There is then oxidized thermally the silicon substrate to form within the trench a thermal silicon oxide trench liner layer. There is then formed upon the thermal silicon oxide trench liner layer a conformal silicon oxide intermediate layer formed through a plasma enhanced chemical vapor deposition (PECVD) method employing a silane silicon source material. Finally, there is then formed upon the conformal silicon oxide intermediate layer a gap filling silicon oxide trench fill layer through an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method employing an ozone oxidant and a tetra-ethyl-ortho-silicate (TEOS) silicon source material. To provide improved properties of the gap filling silicon oxide trench fill layer the thermal silicon oxide trench liner layer may be treated with a nitrogen containing plasma prior to forming the conformal silicon oxide intermediate layer thereupon.

摘要翻译： 一种用于在硅衬底内填充沟槽的方法。 首先提供其中形成有沟槽的硅衬底。 然后将硅衬底热氧化以在沟槽内形成热氧化硅沟槽衬垫层。 然后在热氧化硅沟槽衬垫层上形成通过使用硅烷硅源材料的等离子体增强化学气相沉积（PECVD）方法形成的共形氧化硅中间层。 最后，通过使用臭氧氧化剂和四乙基原硅酸盐的臭氧辅助亚大气压热化学气相沉积（SACVD）方法，在保形氧化硅中间层上形成填充氧化硅沟槽填充层的间隙 （TEOS）硅源材料。 为了提供间隙填充氧化硅沟槽填充层的改进性能，可以在形成其之间的共形氧化硅中间层之前用含氮等离子体处理热氧化硅沟槽衬里层。

公开(公告)号：US5700737A

公开(公告)日：1997-12-23

申请号：US606955

申请日：1996-02-26

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/465

CPC分类号： H01L21/76802 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76885

摘要： This invention provides a method for forming dense electrode patterns having a high aspect ratio in a conductor metal layer. The method uses silicon nitride deposited using plasma enhanced chemical vapor deposition, PECVD, as an etch stop mask to protect the conductor metal and anti reflection coating when etching the electrode patterns. The PECVD silicon nitride is also used a mask to eliminate pattern dependence when forming inter-metal dielectric layers. The PECVD silicon nitride is also used as an etch stop mask when forming vias in the inter-metal dielectric for electrical conduction between electrode pattern layers.

摘要翻译： 本发明提供一种在导体金属层中形成具有高纵横比的致密电极图案的方法。 该方法使用使用等离子体增强化学气相沉积（PECVD）沉积的氮化硅作为蚀刻停止掩模，以在蚀刻电极图案时保护导体金属和抗反射涂层。 当形成金属间介电层时，PECVD氮化硅也被用作掩模以消除图案依赖性。 当在金属间电介质中形成用于电极图案层之间的导电的通孔时，PECVD氮化硅也被用作蚀刻停止掩模。

公开(公告)号：USRE38914E1

公开(公告)日：2005-12-06

申请号：US10329863

申请日：2002-12-26

申请人： Syun-Ming Jang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/3065

CPC分类号： H01L21/76807 ,  H01L2221/1036

摘要： A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate and covering the contact region a blanket first dielectric layer formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed upon the blanket first dielectric layer a blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket hard mask layer a patterned first photoresist layer which leaves exposed a portion of the blanket hard mask layer greater than and completely overlapping an areal deminsion of a via to be formed through the blanket first dielectric layer to access the contact layer. There is then etched while employing a first plasma etch method the blanket hard mask layer to form a patterned hard mask layer defining a first trench formed through the patterned hard mask layer. There is then etched while employing a second plasma etch method and at least the patterned hard mask layer the blanket second dielectric layer to form a patterned second dielectric layer having a second trench formed therethrough, where the second plasma etch method employs the oxygen containing plasma which preferably simultaneously strips the patterned first photoresist layer. There is then formed over at least the patterned second dielectric layer a patterned second photoresist layer which defines the location of the via to be formed through the blanket first dielectric layer. There is then etched while employing a third plasma etch method and the patterned second photoresist layer as a third etch mask layer the via through the blanket first dielectric layer.

公开(公告)号：US06734101B1

公开(公告)日：2004-05-11

申请号：US09998787

申请日：2001-10-31

申请人： Tien-I Bao ,  Jeng Shwang-Ming ,  Syun-Ming Jang ,  Chen-Hua Yu ,  Kuen-Chyr Lee

发明人： Tien-I Bao ,  Jeng Shwang-Ming ,  Syun-Ming Jang ,  Chen-Hua Yu ,  Kuen-Chyr Lee

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76838

摘要： A new method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by: coating an oxide layer over the copper layer and the dielectric layer, thereafter heating the wafer using NH3 plasma, and thereafter depositing a capping layer overlying the oxide layer wherein the time lapse between polishing back the copper layer and depositing the capping layer is less than one day (24 hours).

摘要翻译： 描述了一种在铜金属化中减少铜小丘的新方法。 通过覆盖晶片上的衬底的电介质层形成开口。 形成覆盖在电介质层上并完全填充开口的铜层。 铜层被抛光回去，仅在开口内留下铜层。 通过以下方式减少铜小丘：在氧化层和电介质层上涂覆氧化层，然后使用NH 3等离子体加热晶片，然后沉积覆盖氧化物层的覆盖层，其中抛光铜层和沉积 覆盖层不到一天（24小时）。

公开(公告)号：US06672941B1

公开(公告)日：2004-01-06

申请号：US09696087

申请日：2000-10-26

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： B24B100

CPC分类号： B24B37/013 ,  B24B37/04 ,  B24B37/042 ,  B24B49/16 ,  H01L21/30625

摘要： A method to planarize the surface of a semiconductor substrate having shallow trench isolation (STI) reduces erosion of a silicon nitride planarization stop layer, reduces dishing of large areas of the shallow trench isolation, and prevents under polishing of the surface of the semiconductor substrate that will leave portions of the silicon dioxide that fills the shallow trenches covering the silicon nitride planarization stop exposed, is described. The method to planarize the surface of a semiconductor substrate having shallow trenches begins by chemical/mechanical planarization polishing at a first product of platen pressure and platen speed to planarize the semiconductor substrate. Polishing at a first product of platen pressure and platen speed will cause a high rate of material removal with low selectivity to increase production throughput. The silicon nitride stop layer will be examined to determine an end point exposure of the silicon nitride stop layer. When the end point exposure of the silicon nitride stop layer is reached, chemical/mechanical planarization polishing at a low product of platen pressure and platen speed is started to planarize the semiconductor substrate of slow over polish to control thickness of a trench oxide of the shallow trench isolation to reduce dishing and minimize erosion. The method further has the step of buffing the surface of the semiconductor substrate to remove any residue from the chemical/mechanical planarization polishing and to remove any microscratches from the surface of the semiconductor substrate.

摘要翻译： 平坦化具有浅沟槽隔离（STI）的半导体衬底的表面的方法减少了氮化硅平坦化停止层的侵蚀，减少了大面积浅沟槽隔离的凹陷，并且防止在半导体衬底的表面的抛光 将描述填充覆盖氮化硅平坦化止挡露出的浅沟槽的二氧化硅部分。 平面化具有浅沟槽的半导体衬底的表面的方法开始于在压板压力和压板速度的第一乘积上的化学/机械平面化抛光，以使半导体衬底平坦化。 在压板压力和压板速度的第一个产品上进行抛光将导致高选择性的材料去除率，从而提高生产量。 将检查氮化硅阻挡层以确定氮化硅阻挡层的端点暴露。 当达到氮化硅终止层的终点曝光时，开始以压板压力和压板速度的低乘积进行化学/机械平面化抛光，以平缓化缓慢过抛光的半导体衬底，以控制浅层的沟槽氧化物的厚度 沟槽隔离以减少凹陷和最小化侵蚀。 该方法还具有抛光半导体衬底的表面以从化学/机械平面化抛光中除去任何残余物并从半导体衬底的表面去除任何微细凹凸的步骤。

公开(公告)号：US06599847B1

公开(公告)日：2003-07-29

申请号：US08697699

申请日：1996-08-27

申请人： Syun-Ming Jang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21469

CPC分类号： H01L21/02164 ,  C23C16/401 ,  C23C16/505 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31612 ,  H01L21/76801 ,  H01L21/76837

摘要： A method for forming for use within an integrated circuit a gap filling sandwich composite dielectric layer construction, and an integrated circuit having formed therein the gap filling sandwich composite dielectric layer construction. To practice the method, there is first provided a substrate having formed thereover a patterned layer. There is then formed upon the patterned layer a first conformal dielectric layer through a first plasma enhanced chemical vapor deposition (PECVD) method employing a first radio frequency power optimized primarily to limit plasma induced damage to the substrate and the patterned layer. The first radio frequency power is also optimized secondarily to limit moisture permeation through the first conformal dielectric layer. There is then formed upon the first conformal dielectric layer a gap filling dielectric layer. Finally, there is formed upon the gap filling dielectric layer a second conformal dielectric layer through a second plasma enhanced chemical vapor deposition (PECVD) method employing a second radio frequency power optimized primarily to limit moisture permeation through the second conformal dielectric layer.

摘要翻译： 一种用于在集成电路内使用间隙填充夹层复合电介质层结构的形成方法，以及在其中形成间隙填充夹心复合电介质层结构的集成电路。 为了实施该方法，首先提供了在其上形成图案化层的衬底。 然后，通过采用首先优化的第一射频功率的第一等离子体增强化学气相沉积（PECVD）方法，在图案化层上形成第一共形介电层，该第一射频功率主要是为了限制对衬底和图案化层的等离子体引起的损伤。 第一射频功率也被二次优化以限制通过第一保形介电层的水分渗透。 然后在第一保形介电层上形成间隙填充介电层。 最后，通过第二等离子体增强化学气相沉积（PECVD）方法在间隙上填充介电层形成第二共形介电层，所述第二等离子体增强化学气相沉积（PECVD）方法采用主要优化通过第二共形介电层来限制水分渗透的第二射频功率。

公开(公告)号：US06436771B1

公开(公告)日：2002-08-20

申请号：US09902895

申请日：2001-07-12

申请人： Syun-Ming Jang ,  Chen-Hua Yu ,  Mong-Song Liang

发明人： Syun-Ming Jang ,  Chen-Hua Yu ,  Mong-Song Liang

IPC分类号： H01L218234

CPC分类号： H01L21/823462 ,  Y10S438/981

摘要： Process sequences used to simultaneously form a first dielectric gate layer for a first group of MOSFET elements, and a second dielectric gate layer for a second group of MOSFET elements, with the thickness of the first dielectric gate layer different than the thickness of the second gate dielectric layer, has been developed. A first iteration of this invention entails a remote plasma nitridization procedure used to form a thin silicon nitride layer on a bare, first portion of a semiconductor substrate, while simultaneously forming a thin silicon oxynitride layer on the surface of a first silicon dioxide layer, located on second portion of the semiconductor substrate. A thermal oxidation procedure than results in the formation of a thin second silicon dioxide layer, on the first portion of the semiconductor substrate, underlying the thin silicon nitride layer, while the first silicon dioxide layer, underlying the silicon oxynitride component of the composite dielectric layer, only increases slightly in thickness. A second iteration of this invention features the formation of a silicon nitride—first silicon dioxide, composite gate layer, on a first portion of a semiconductor substrate, with the composite gate layer used to retard oxidation during a thermal oxidation procedure used growth to form a second silicon dioxide layer, on a second portion of the semiconductor substrate.

摘要翻译： 用于同时形成用于第一组MOSFET元件的第一电介质栅极层和用于第二组MOSFET元件的第二电介质栅极层的工艺序列，其中第一电介质栅极层的厚度不同于第二栅极的厚度 电介质层，已经开发。 本发明的第一次迭代需要用于在半导体衬底的裸露的第一部分上形成薄氮化硅层的远程等离子体氮化过程，同时在第一二氧化硅层的表面上形成薄的氮氧化硅层，所述第一二氧化硅层位于 在半导体衬底的第二部分上。 一种热氧化方法，其结果是在半导体衬底的第一部分上形成薄的第二二氧化硅层，位于薄氮化硅层下面，同时第一二氧化硅层位于复合介电层的氮氧化硅组分下面 ，厚度仅略有增加。 本发明的第二次迭代的特征在于在半导体衬底的第一部分上形成氮化硅 - 第一二氧化硅复合栅极层，其中用于在热氧化过程中延迟氧化的复合栅极层用于生长以形成 第二二氧化硅层，在半导体衬底的第二部分上。

公开(公告)号：US06423625B1

公开(公告)日：2002-07-23

申请号：US09385754

申请日：1999-08-30

申请人： Syun-Ming Jang ,  Mong-Song Liang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Jane-Bai Lai

发明人： Syun-Ming Jang ,  Mong-Song Liang ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Jane-Bai Lai

IPC分类号： H01L2160

CPC分类号： H01L24/05 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/11 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05001 ,  H01L2224/05006 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

摘要： Cu, for its rather loe resistivity, will be widely used in sub-quarter micron meter ULSI devices. However, it is well known that Cu is easy to be corroded as exposed in air. In packaging of chips the bonding pads making of Cu will thus oxides. In addition, the reaction between Au-ball and Cu pads is very poor. On the other hand, a native AlOx layer, about 3-4 nm in thickness, will form as Al exposes in air; the formed layer is inert and is capable of protecting Al from corrosion. Furthermore, the reaction between Au-ball and Al was very well. Therefore, with the methods of the present invention, Al or AlCu as a glue and protection layer is implemented on Cu bonding pads for successful Au wiring.

摘要翻译： 铜，因其相当的电阻率，将广泛应用于二分之一微米级ULSI器件。 然而，众所周知，Cu在空气中容易被腐蚀。 在芯片的封装中，由此制成Cu的焊盘将氧化。 此外，Au球和Cu垫之间的反应非常差。 另一方面，厚度约3-4nm的天然AlOx层将在Al中暴露于空气中形成; 形成的层是惰性的并且能够保护Al免于腐蚀。 此外，Au球和Al之间的反应非常好。 因此，利用本发明的方法，在用于成功的Au布线的Cu焊盘上实施作为胶水和保护层的Al或AlCu。

公开(公告)号：US06372664B1

公开(公告)日：2002-04-16

申请号：US09419104

申请日：1999-10-15

申请人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chu-Yun Fu ,  Chen-Hua Yu

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/31612 ,  H01L21/76801

摘要： A method for forming upon a substrate employed within a microelectronics fabrication a dieletric layer with improved physical properties. There is first provided a substrate. There is then formed over the substrate a series of lines which constitute a patterned microelectronics layer. There is then formed over the patterned microelectronics layer and substrate a conformal dielectric layer. There is then formed over the substrate a second dielectric layer. There is then formed over the substrate a third dielectric layer formed of silicon oxide dielectric material employing high density plasma chemical vapor deposition (HDP-CVD) to complete a composite inter-level metal dielectric (IMD) layer. A fourth dielectric layer formed employing silicon containing dielectric material may be formed over the substrate and third dielectric layer to complete an inter-level metal dielectric (IMD) layer. The fourth dielectric layer is inhibited from cracking by the presence of the third silicon oxide dielectric layer formed by HDP-CVD method.

摘要翻译： 一种用于在微电子制造中使用的衬底上形成具有改进的物理性质的抗蚀层的方法。 首先提供基板。 然后在衬底上形成构成图案化微电子层的一系列线。 然后在图案化的微电子层和衬底上形成共形介电层。 然后在衬底上形成第二介电层。 然后在衬底上形成由使用高密度等离子体化学气相沉积（HDP-CVD）的氧化硅介电材料形成的第三介电层，以完成复合层间金属电介质（IMD）层。 可以在衬底和第三电介质层上形成使用含硅电介质材料形成的第四电介质层，以完成层间金属电介质（IMD）层。 通过存在由HDP-CVD法形成的第三氧化硅电介质层，可以抑制第四绝缘层的破裂。

公开(公告)号：US06329717B1

公开(公告)日：2001-12-11

申请号：US08616140

申请日：1996-03-14

申请人： Syun-Ming Jang ,  Chen-Hua Yu ,  Lung Chen ,  Lin-June Wu

发明人： Syun-Ming Jang ,  Chen-Hua Yu ,  Lung Chen ,  Lin-June Wu

IPC分类号： H01L2348

CPC分类号： H01L21/76801

摘要： A method for selectively depositing a silicon oxide insulator spacer layer between multi-layer patterned metal stacks within an integrated circuit. Formed upon a semiconductor substrate is a silicon oxide insulator substrate layer which is formed through a Plasma Enhanced Chemical Vapor Deposition (PECVD) process. Upon the silicon oxide insulator substrate layer are formed multi-layer patterned metal stacks. The multi-layer patterned metal stacks have a top barrier metal layer formed from titanium nitride and a lower-lying conductor metal layer formed from an aluminum containing alloy. Formed selectively upon the portions of the silicon oxide insulator substrate layer exposed through the multi-layer patterned metal stacks and upon the edges of the aluminum containing alloy exposed through the multi-layer patterned metal stacks is a silicon oxide insulator spacer layer. The silicon oxide insulator spacer layer is formed through an ozone assisted Chemical Vapor Deposition (CVD) process employing Tetra Ethyl Ortho Silicate as the silicon source material. The silicon oxide insulator spacer layer is formed for a deposition time not exceeding an incubation time for forming the silicon oxide insulator spacer layer upon the top barrier metal layer formed from titanium nitride.

摘要翻译： 一种用于在集成电路内的多层图案化金属堆叠之间选择性地沉积氧化硅绝缘体间隔层的方法。 形成在半导体衬底上的是通过等离子体增强化学气相沉积（PECVD）工艺形成的氧化硅绝缘体衬底层。 在氧化硅绝缘体衬底层形成多层图案化的金属叠层时。 多层图案化的金属堆叠具有由氮化钛形成的顶部阻挡金属层和由含铝合金形成的下部导体金属层。 在通过多层图案化的金属堆叠暴露的氧化硅绝缘体基底层的部分上并且通过多层图案化的金属堆叠暴露的含铝合金的边缘上选择性地形成氧化硅绝缘体间隔层。 氧化硅绝缘体间隔层通过使用四乙基正硅酸盐作为硅源材料的臭氧辅助化学气相沉积（CVD）工艺形成。 形成氧化硅绝缘体间隔层，用于在由氮化钛形成的顶部阻挡金属层上形成氧化硅绝缘体间隔层的沉积时间不超过孵育时间。