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    Method of forming a semiconductor device with multiple thickness gate dielectric layers
    1.
    发明授权
    Method of forming a semiconductor device with multiple thickness gate dielectric layers 有权
    形成具有多个厚度栅极电介质层的半导体器件的方法

    公开(公告)号：US06436771B1

    公开(公告)日：2002-08-20

    申请号：US09902895

    申请日：2001-07-12

    申请人： Syun-Ming Jang ,  Chen-Hua Yu ,  Mong-Song Liang

    发明人： Syun-Ming Jang ,  Chen-Hua Yu ,  Mong-Song Liang

    IPC分类号： H01L218234

    CPC分类号： H01L21/823462 ,  Y10S438/981

    摘要： Process sequences used to simultaneously form a first dielectric gate layer for a first group of MOSFET elements, and a second dielectric gate layer for a second group of MOSFET elements, with the thickness of the first dielectric gate layer different than the thickness of the second gate dielectric layer, has been developed. A first iteration of this invention entails a remote plasma nitridization procedure used to form a thin silicon nitride layer on a bare, first portion of a semiconductor substrate, while simultaneously forming a thin silicon oxynitride layer on the surface of a first silicon dioxide layer, located on second portion of the semiconductor substrate. A thermal oxidation procedure than results in the formation of a thin second silicon dioxide layer, on the first portion of the semiconductor substrate, underlying the thin silicon nitride layer, while the first silicon dioxide layer, underlying the silicon oxynitride component of the composite dielectric layer, only increases slightly in thickness. A second iteration of this invention features the formation of a silicon nitride—first silicon dioxide, composite gate layer, on a first portion of a semiconductor substrate, with the composite gate layer used to retard oxidation during a thermal oxidation procedure used growth to form a second silicon dioxide layer, on a second portion of the semiconductor substrate.

    摘要翻译： 用于同时形成用于第一组MOSFET元件的第一电介质栅极层和用于第二组MOSFET元件的第二电介质栅极层的工艺序列，其中第一电介质栅极层的厚度不同于第二栅极的厚度 电介质层，已经开发。 本发明的第一次迭代需要用于在半导体衬底的裸露的第一部分上形成薄氮化硅层的远程等离子体氮化过程，同时在第一二氧化硅层的表面上形成薄的氮氧化硅层，所述第一二氧化硅层位于 在半导体衬底的第二部分上。 一种热氧化方法，其结果是在半导体衬底的第一部分上形成薄的第二二氧化硅层，位于薄氮化硅层下面，同时第一二氧化硅层位于复合介电层的氮氧化硅组分下面 ，厚度仅略有增加。 本发明的第二次迭代的特征在于在半导体衬底的第一部分上形成氮化硅 - 第一二氧化硅复合栅极层，其中用于在热氧化过程中延迟氧化的复合栅极层用于生长以形成 第二二氧化硅层，在半导体衬底的第二部分上。

    Diffusion inhibited dielectric structure for diffusion enhanced conductor layer
    4.
    发明授权
    Diffusion inhibited dielectric structure for diffusion enhanced conductor layer 有权
    扩散抑制扩散增强导体层的电介质结构

    公开(公告)号：US06368952B1

    公开(公告)日：2002-04-09

    申请号：US09638775

    申请日：2000-08-15

    申请人： Mong-Song Liang ,  Syun-Ming Jang

    发明人： Mong-Song Liang ,  Syun-Ming Jang

    IPC分类号： H01L274736

    CPC分类号： H01L21/76801 ,  H01L23/49894 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Within a method for forming a microelectronic fabrication, there is first provided a substrate. There is then formed over the substrate a microelectronic device passivated with a patterned first dielectric layer in turn annularly surrounded by a patterned second dielectric layer. There is also formed over the substrate a patterned conductor layer separated from the microelectronic device by the patterned first dielectric layer and the patterned second dielectric layer. Within the method: (1) the patterned first dielectric layer is formed from a first dielectric material having a first diffusion coefficient with respect to a conductor material from which is formed the patterned conductor layer; (2) the patterned second dielectric layer is formed from a second dielectric material having a second diffusion coefficient with respect to the conductor material from which is formed the patterned conductor layer; and (3) the first diffusion coefficient is greater than the second diffusion coefficient.

    摘要翻译： 在用于形成微电子制造的方法中，首先提供衬底。 然后在衬底上形成钝化了图案化的第一介电层的微电子器件，然后被图案化的第二介电层环绕地环绕。 还在衬底上形成通过图案化的第一介电层和图案化的第二介电层与微电子器件分离的图案化导体层。 在该方法中：（1）图案化的第一介电层由相对于形成图案化导体层的导体材料具有第一扩散系数的第一介电材料形成; （2）图案化的第二电介质层由相对于形成图案化导体层的导体材料具有第二扩散系数的第二电介质材料形成; 和（3）第一扩散系数大于第二扩散系数。

    Method for forming a ultra-thin gate insulator layer
    5.
    发明授权
    Method for forming a ultra-thin gate insulator layer 有权
    用于形成超薄栅极绝缘体层的方法

    公开(公告)号：US06184155B2

    公开(公告)日：2001-02-06

    申请号：US09596902

    申请日：2000-06-19

    申请人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Mong-Song Liang

    发明人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Mong-Song Liang

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  H01L21/28211 ,  H01L21/31662

    摘要： A process for forming an ultra-thin, silicon dioxide, gate insulator layer, for narrow channel length MOSFET devices, has been developed. The process features the use of a two step, in situ steam generated, (ISSG), procedure, to grow a silicon dioxide layer at a physical thickness between about 10 to 20 Angstroms, offering a gate insulator layer with a reduction in leakage current, during standby, or operating modes, when compared to counterpart silicon dioxide layers, formed without the use of the two step, ISSG procedure. The two step, ISSG procedure is comprised of a first step, featuring a steam oxidation, and an in situ anneal, in a nitrous oxide ambient, followed by the second step of the two step, ISSG procedure, performed in situ, in the same furnace used for the first step of the two step, ISSG procedure, with the second step of the two step, ISSG procedure again comprised of a steam oxidation, followed by an in situ anneal, performed in a nitrous oxide ambient.

    摘要翻译： 已经开发了用于形成用于窄沟道长度MOSFET器件的超薄二氧化硅栅极绝缘体层的工艺。 该方法的特征在于使用两步，原位蒸汽生成（ISSG）方法，以在约10至20埃之间的物理厚度生长二氧化硅层，从而提供具有减小的漏电流的栅极绝缘体层， 在待机或操作模式下，与对应的二氧化硅层进行比较时，不使用两步即可形成ISSG程序。 两步ISSG程序包括第一步，其特征在于在一氧化二氮环境中进行蒸汽氧化和原位退火，随后是两步的第二步，ISSG程序，原位进行，在相同的 炉用于两步的第一步，ISSG程序，第二步是两步，ISSG程序再次由蒸汽氧化组成，随后在一氧化二氮环境中进行原位退火。

    Laminating method for forming integrated circuit microelectronic fabrication
    9.
    发明授权
    Laminating method for forming integrated circuit microelectronic fabrication 有权
    用于形成集成电路微电子制造的层压方法

    公开(公告)号：US06740567B2

    公开(公告)日：2004-05-25

    申请号：US09885784

    申请日：2001-06-20

    申请人： Mong-Song Liang ,  Syun-Ming Jang

    发明人： Mong-Song Liang ,  Syun-Ming Jang

    IPC分类号： H01L2130

    CPC分类号： H01L21/768 ,  H01L23/522 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00

    摘要： Within a method for fabricating a semiconductor integrated circuit microelectronic fabrication there is first provided a first semiconductor substrate. There is then formed over the first semiconductor substrate at least one microelectronic device to form from the first semiconductor substrate a partially fabricated semiconductor integrated circuit microelectronic fabrication. Within the method there is also provided a second substrate. There is also formed over the second substrate, in inverted order, a dielectric isolated metallization pattern intended to mate with the partially fabricated semiconductor integrated circuit microelectronic fabrication. Finally, there is then laminated the partially fabricated semiconductor integrated circuit microelectronic fabrication with the second substrate to mate the partially fabricated semiconductor integrated circuit microelectronic fabrication with the dielectric isolated metallization pattern to thus form a laminated completely fabricated semiconductor integrated circuit microelectronic fabrication. The method provides for enhanced efficiency when fabricating semiconductor integrated circuit microelectronic fabrications.

    摘要翻译： 在制造半导体集成电路微电子制造的方法中，首先提供第一半导体衬底。 然后在第一半导体衬底上形成至少一个微电子器件，以从第一半导体衬底形成部分制造的半导体集成电路微电子制造。 在该方法中，还提供了第二衬底。 在第二衬底上还以反向顺序形成旨在与部分制造的半导体集成电路微电子制造配合的电介质隔离金属化图案。 最后，然后将部分制造的半导体集成电路微电子制造与第二衬底层压，以将部分制造的半导体集成电路微电子制造与介电隔离金属化图案配合，从而形成层叠的完全制造的半导体集成电路微电子制造。 该方法在制造半导体集成电路微电子制造时提供了增强的效率。

    Fabrication of MIM capacitor in copper damascene process
    10.
    发明授权
    Fabrication of MIM capacitor in copper damascene process 有权
    铜电镀工艺中MIM电容器的制造

    公开(公告)号：US06387775B1

    公开(公告)日：2002-05-14

    申请号：US09835025

    申请日：2001-04-16

    申请人： Syun-Ming Jang ,  Mong-Song Liang

    发明人： Syun-Ming Jang ,  Mong-Song Liang

    IPC分类号： H01L2120

    CPC分类号： H01L28/60 ,  H01L21/31116 ,  H01L21/31604 ,  H01L21/76802 ,  H01L28/56

    摘要： A method for forming an MIM capacitor, comprising the following steps. A semiconductor structure having an exposed lower metal damascene is provided. A capacitor layer is formed over the semiconductor structure and the exposed lower metal damascene. An organic etch stop layer is formed upon the capacitor layer. An IMD layer is formed upon the organic etch stop layer. The IMD layer is etched with a first etch highly selective to the IMD layer as compared to the organic etch stop layer, to form an IMD trench exposing a portion of the organic etch stop layer. The exposed portion of the organic etch stop layer is etched with a second etch method highly selective to the exposed portion of the organic etch stop layer as compared to the capacitor layer, to expose a portion of the capacitor layer. An upper metal damascene is formed upon the exposed portion of the capacitor layer and within the IMD trench to complete formation of the MIM capacitor.

    摘要翻译： 一种用于形成MIM电容器的方法，包括以下步骤。 提供具有暴露的下金属镶嵌的半导体结构。 在半导体结构和暴露的下金属镶嵌件上形成电容器层。 在电容器层上形成有机蚀刻停止层。 在有机蚀刻停止层上形成IMD层。 与有机蚀刻停止层相比，以IMD层高度选择性的第一蚀刻蚀刻IMD层，以形成暴露部分有机蚀刻停止层的IMD沟槽。 与电容器层相比，用有机​​蚀刻停止层的暴露部分高度选择性的第二蚀刻方法蚀刻有机蚀刻停止层的暴露部分，以暴露电容器层的一部分。 在电容器层的暴露部分和IMD沟槽内形成上金属镶嵌，以完成MIM电容器的形成。