公开(公告)号：US20070181951A1

公开(公告)日：2007-08-09

申请号：US11349804

申请日：2006-02-08

Applicant: Chia-Lin Chen ,  Min-Jan Chen ,  Jau-Jey Wang

Inventor： Chia-Lin Chen ,  Min-Jan Chen ,  Jau-Jey Wang

IPC: H01L29/76 ,  H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

Abstract translation: 提供了较少受负偏压时间不稳定性（NBTI）影响的PMOS器件及其形成方法。 PMOS器件在PMOS器件的栅极结构，栅极间隔物和源极/漏极区域的至少一部分上包括阻挡层。 然后在阻挡层上形成应力层。 阻挡层优选为氧化物层，优选不为NMOS器件形成。

公开(公告)号：US07118974B2

公开(公告)日：2006-10-10

申请号：US10831871

申请日：2004-04-26

Applicant: Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

Inventor： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC: H01L21/336

CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

Abstract: A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

公开(公告)号：US20050159008A1

公开(公告)日：2005-07-21

申请号：US10758317

申请日：2004-01-15

Applicant: Vincent Chang ,  Chia-Lin Chen ,  Chi-Chun Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Chien-Hao Chen

Inventor： Vincent Chang ,  Chia-Lin Chen ,  Chi-Chun Chen ,  Tze-Liang Lee ,  Shih-Chang Chen ,  Chien-Hao Chen

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/314 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/477 ,  H01L29/51

CPC classification number: H01L29/518 ,  H01L21/28123 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/32137 ,  H01L29/6659

Abstract: A method of defining a conductive gate structure for a MOSFET device wherein the etch rate selectivity of the conductive gate material to an underlying insulator layer is optimized, has been developed. After formation of a nitrided silicon dioxide layer, to be used as for the MOSFET gate insulator layer, a high temperature hydrogen anneal procedure is performed. The high temperature anneal procedure replaces nitrogen components in a top portion of the nitrided silicon dioxide gate insulator layer with hydrogen components. The etch rate of the hydrogen annealed layer in specific dry etch ambients is now decreased when compared to the non-hydrogen annealed nitrided silicon dioxide counterpart. Thus the etch rate selectivity of conductive gate material to underlying gate insulator material is increased when employing the slower etching hydrogen annealed nitrided silicon dioxide layer.

Abstract translation: 已经开发了限定用于MOSFET器件的导电栅极结构的方法，其中导电栅极材料对下面的绝缘体层的蚀刻速率选择性被优化。 在形成用于MOSFET栅极绝缘体层的氮化二氧化硅层之后，进行高温氢退火处理。 高温退火程序用氢组分替代氮化二氧化硅栅极绝缘体层的顶部中的氮组分。 当与非氢退火氮化二氧化硅对应物相比时，特定干蚀刻环境中的氢退火层的蚀刻速率现在降低。 因此，当采用较慢的蚀刻氢退火氮化二氧化硅层时，导电栅极材料对底层栅极绝缘体材料的蚀刻速率选择性增加。

公开(公告)号：US06830996B2

公开(公告)日：2004-12-14

申请号：US10395345

申请日：2003-03-24

Applicant: Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen

Inventor： Chia-Lin Chen ,  Tze Liang Lee ,  Shih-Chang Chen

IPC: H01L213205

CPC classification number: H01L21/28202 ,  H01L21/02052 ,  H01L21/321 ,  H01L29/518

Abstract: The present disclosure provides a method is provided for fabricating a metal oxide semiconductor (MOS) gate stack on a semiconductor substrate. The method includes generating moisture on a surface of the semiconductor substrate to form an oxide layer less than 10 nanometers thin and performing a nitridation process on the thin oxide layer. After the nitridation process, the method includes performing a polysilicon deposition process on the surface of the semiconductor substrate, doping the polysilicon deposition to a level of 5×1015 at/cm3, and cleaning the doped polysilicon with a light ammonia solution.

Abstract translation: 本公开提供了一种用于在半导体衬底上制造金属氧化物半导体（MOS）栅极堆叠的方法。 该方法包括在半导体衬底的表面上产生湿气以形成小于10纳米薄的氧化物层，并对薄氧化物层进行氮化处理。 在氮化处理之后，该方法包括在半导体衬底的表面上执行多晶硅沉积工艺，将多晶硅沉积掺杂至5×10 15 at / cm 3的水平，并用轻氨溶液清洗掺杂的多晶硅。

公开(公告)号：USD960573S1

公开(公告)日：2022-08-16

申请号：US29737818

申请日：2020-06-11

Applicant: Chia-Lin Chen

Designer： Chia-Lin Chen

公开(公告)号：US09406825B2

公开(公告)日：2016-08-02

申请号：US14720188

申请日：2015-05-22

Applicant: Chia-Lin Chen

Inventor： Chia-Lin Chen

IPC: H01L31/00 ,  H01L31/043 ,  H01L31/0445 ,  H01L31/054

CPC classification number: H01L31/0543 ,  H02S40/22 ,  Y02E10/52

Abstract: A stacked and integrated electric power generating device for capturing multiple light sources for power generation has a first concentrating photovoltaic module and a second concentrating photovoltaic module. The first concentrating photovoltaic module 10 has a transparent solar concentrating panel and a thin film solar cell. The second concentrating photovoltaic module is positioned below the first concentrating photovoltaic module with an interval, such that the first and second concentrating photovoltaic modules are in the form of a stacked and integrated structure, and the second concentrating photovoltaic module can absorb the light concentrated by the transparent solar concentrating panel to generate electric power.

Abstract translation: 用于捕获用于发电的多个光源的堆叠和集成的发电装置具有第一集中光伏模块和第二集中光伏模块。 第一聚光光伏模块10具有透明太阳能集中板和薄膜太阳能电池。 第二集中光伏模块以一定的间隔位于第一聚光光伏模块的下方，使得第一和第二集中光伏模块呈堆叠且一体化的结构，第二聚光光伏模块可以吸收由 透明的太阳能集中板产生电力。

公开(公告)号：US08889507B2

公开(公告)日：2014-11-18

申请号：US11765971

申请日：2007-06-20

Applicant: Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

Inventor： Chih-Ta Wu ,  Jason Lee ,  Chung Chien Wang ,  Hsing-Lien Lin ,  Yu-Jen Wang ,  Yeur-Luen Tu ,  Chern-Yow Hsu ,  Yuan-Hung Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Lucy Chang ,  Chia-Lin Chen ,  Ming-Chih Tsai

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L49/02 ,  H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/75

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract translation: 提供电容器及其形成方法。 该方法包括形成底部电极; 在含氧环境中处理底部电极以将底部电极的顶层转化为缓冲层; 在缓冲层上形成绝缘层; 并在所述绝缘层上形成顶部电极。

公开(公告)号：US20080236218A1

公开(公告)日：2008-10-02

申请号：US11694080

申请日：2007-03-30

Applicant: Chia-Lin Chen

Inventor： Chia-Lin Chen

IPC: B60R25/02

CPC classification number: B60R25/0225 ,  Y10T70/5765

Abstract: A steering wheel locking device includes a lock rod, a lock base, a locking device and a fixing unit. The lock rod has a chamber, two pairs of first holes longitudinally aligned, a lock hole and a saddle. The lock base comprises a lock core to be inserted into the lock base through the lock hole. The top of the lock core is provided with a latch. The locking device has a pair of second holes in register with the pairs of first holes of the lock rod, and is engageable with the latch and moveable transversely along the lock rod between a locked position and an unlocked position. The fixing unit comprises a pair of fixing rods in register with the pairs of first holes of the lock rod and the pair of second holes of the locking device. The fixing rods are moveable longitudinally through the pairs of first holes and the pair of second holes to lock or unlock the locking device.

Abstract translation: 方向盘锁定装置包括锁定杆，锁定基座，锁定装置和固定单元。 锁杆具有一个腔室，两对纵向排列的第一孔，一个锁孔和一个鞍座。 锁定基座包括通过锁定孔插入到锁定基座中的锁芯。 锁芯的顶部设有闩锁。 锁定装置具有与锁定杆的成对的第一孔对准的一对第二孔，并且能够与闩锁接合并且可在锁定位置和解锁位置之间沿着锁定杆横向移动。 定影单元包括一对与锁定杆的成对的第一孔对准的固定杆和锁定装置的一对第二孔。 固定杆可纵向移动穿过成对的第一孔和一对第二孔，以锁定或解锁锁定装置。

公开(公告)号：US20080157266A1

公开(公告)日：2008-07-03

申请号：US12049452

申请日：2008-03-17

Applicant: Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

Inventor： Chien-Hao Chen ,  Vincent S. Chang ,  Chia-Lin Chen ,  Tze-Liang Lee ,  Shih-Chang Chen

IPC: H01L21/762

CPC classification number: H01L21/76235

Abstract: A new and improved liner modification method for a liner oxide layer in an STI trench is disclosed. According to the method, an STI trench is etched in a substrate and a liner oxide layer is formed on the trench surfaces by oxidation techniques. The method further includes pre-treatment of the trench surfaces using a nitrogen-containing gas prior to formation of the liner oxide layer, post-formation nitridation of the liner oxide layer, or both pre-treatment of the trench surfaces and post-formation nitridation of the liner oxide layer. The liner modification method of the present invention optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of STI structures and prevents diffusion of dopant into the liner oxide layer during subsequent processing.

Abstract translation: 公开了一种用于STI沟槽中的衬垫氧化物层的新的改进的衬垫修改方法。 根据该方法，在衬底中蚀刻STI沟槽，并且通过氧化技术在沟槽表面上形成衬垫氧化物层。 该方法还包括在形成衬垫氧化物层之前使用含氮气体预处理沟槽表面，衬里氧化物层的形成后氮化或沟槽表面的预处理和后形成氮化 的衬里氧化物层。 本发明的衬垫修改方法优化STI结构的反窄窄度效应（INWE）和栅极氧化物完整性（GOI），并防止掺杂剂在随后的处理期间扩散到衬里氧化物层中。

公开(公告)号：US07138317B2

公开(公告)日：2006-11-21

申请号：US10831874

申请日：2004-04-26

Applicant: Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

Inventor： Chia-Lin Chen ,  Chien-Hao Chen ,  Mo-Chiun Yu

IPC: H01L21/8234

CPC classification number: H01L21/823857 ,  H01L21/28202 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823878 ,  Y10S438/981

Abstract: A method of forming multiple gate oxide thicknesses on active areas that are separated by STI isolation regions on a substrate. A first layer of oxide is grown to a thickness of about 50 Angstroms and selected regions are then removed. A second layer of oxide is grown that is thinner than first growth oxide. For three different gate oxide thicknesses, selected second oxide growth regions are nitridated with a N2 plasma which increases the dielectric constant of a gate oxide and reduces the effective oxide thickness. To achieve four different gate oxide thicknesses, nitridation is performed on selected first growth oxides and on selected second growth oxide regions. Nitridation of gate oxides also prevents impurity dopants from migrating across the gate oxide layer and reduces leakage of standby current. The method also reduces corner loss of STI regions caused by HF etchant.

Abstract translation: 在由衬底上的STI隔离区隔开的有源区上形成多个栅极氧化物厚度的方法。 将第一层氧化物生长至约50埃的厚度，然后除去选定的区域。 生长比第一生长氧化物薄的第二层氧化物。 对于三种不同的栅极氧化物厚度，选择的第二氧化物生长区域用N 2 O 3等离子体氮化，这增加了栅极氧化物的介电常数并降低了有效的氧化物厚度。 为了实现四种不同的栅极氧化物厚度，对所选择的第一生长氧化物和选择的第二生长氧化物区域进行氮化。 栅极氧化物的氮化还防止杂质掺杂剂跨过栅极氧化物层迁移并减少待机电流的泄漏。 该方法还减少由HF蚀刻剂引起的STI区域的拐角损失。