公开(公告)号：US4985717A

公开(公告)日：1991-01-15

申请号：US313648

申请日：1989-02-21

Applicant: Sheldon Aronowitz ,  Donald D. Forsythe ,  George P. Walker ,  Bhaskar V. S. Gadepally

Inventor： Sheldon Aronowitz ,  Donald D. Forsythe ,  George P. Walker ,  Bhaskar V. S. Gadepally

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/10 ,  H01L29/36 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/1041 ,  H01L29/36 ,  H01L29/7881

Abstract: A semiconductor memory device having a CMOS memory cell with a floating gate and increasing concentration of dopant in the source, drain and channel regions. Typically the concentration profile is generally exponential across the channel width. The device has relatively high diffusion current densities accelerated toward the surface and directed toward the channel/drain interface. Gate oxidation thickness is reduced over the channel near the drain to create a tunnel "window" in the area of greatest electric field magnitude. The device provides for significantly reduced write times as compared to conventional devices.

公开(公告)号：US07323228B1

公开(公告)日：2008-01-29

申请号：US10697506

申请日：2003-10-29

Applicant: Sheldon Aronowitz ,  James Kimball

Inventor： Sheldon Aronowitz ,  James Kimball

IPC: B05D3/06

CPC classification number: C23C14/18 ,  C23C14/228

Abstract: Techniques for vaporizing and handling a vaporized metallic element or metallic element salt with a heated inert carrier gas for further processing. The vaporized metallic element or salt is carried by an inert carrier gas heated to the same temperature as the vaporizing temperature to a heated processing chamber. The metal or salt vapor may be ionized (and implanted) or deposited on substrates. Apparatus for accomplishing these techniques, which include carrier gas heating chambers and heated processing chambers are also provided.

Abstract translation: 用加热的惰性载气汽化和处理蒸发的金属元素或金属元素盐进行进一步处理的技术。 蒸发的金属元素或盐由加热至与蒸发温度相同的温度的惰性载气携带到加热的处理室。 金属或盐蒸气可以离子化（和注入）或沉积在基底上。 还提供了用于实现这些技术的装置，其包括载气加热室和加热处理室。

公开(公告)号：US06919263B2

公开(公告)日：2005-07-19

申请号：US10643687

申请日：2003-08-19

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace Sun

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Grace Sun

IPC: C23C16/40 ,  C23C16/44 ,  H01L21/28 ,  H01L21/316 ,  H01L29/51 ,  H01L21/3205

CPC classification number: H01L29/517 ,  C23C16/40 ,  H01L21/28194 ,  H01L21/31604 ,  H01L21/31683

Abstract: A new relatively high-k gate dielectric gate material comprising calcium oxide will reduce leakage from the silicon substrate to the polysilicon gate, prevent boron penetration in p-channel devices, and reduce electron trapping in the dielectric. The surface of a silicon wafer is saturated with hydroxyl groups. A calcium halide, preferably calcium bromide, is heated to a temperature sufficient to achieve atomic layer deposition, and is transported to the silicon wafer. The calcium halide reacts with the hydroxyl groups. Water is added to carry away the resultant hydrogen halide. Gaseous calcium and water are then added to form a calcium oxide gate dielectric, until the desired thickness has been achieved. In an alternative embodiment of the method, the calcium halide is transported to the silicon wafer to react with the hydroxyl groups, followed by transport of gaseous water to the silicon wafer. These two steps are repeated until the desired thickness has been achieved.

Abstract translation: 包含氧化钙的新的相对高k的栅介质栅极材料将减少从硅衬底到多晶硅栅极的泄漏，防止在p沟道器件中的硼渗透，并减少电介质中的电子俘获。 硅晶片的表面被羟基饱和。 将卤化钙，优选溴化钙加热到足以实现原子层沉积的温度，并被输送到硅晶片。 卤化钙与羟基反应。 加入水以携带所得的卤化氢。 然后加入气态钙和水以形成氧化钙栅极电介质，直至达到所需的厚度。 在该方法的替代实施方案中，将卤化钙输送到硅晶片以与羟基反应，然后将气态水输送到硅晶片。 重复这两个步骤，直到达到所需的厚度。

公开(公告)号：US06858195B2

公开(公告)日：2005-02-22

申请号：US09792685

申请日：2001-02-23

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: C23C16/40 ,  C01B33/12

CPC classification number: C23C16/401 ,  Y10T428/30

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes selected from: (a) an organofluoro silane containing two silicon atoms linked by one oxygen atom; (b) an organofluoro silane containing two silicon atoms linked by one or more carbon atoms, where the one or more carbon atoms each are bonded to one or more fluorine atoms, or to one or more organofluoro moieties, or to a combination thereof; and (c) an organofluoro silane containing a silicon atom bonded to an oxygen atom. The invention also provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes characterized by the presence of Si—O bonds.

Abstract translation: 本发明提供了一种通过与氧化剂反应形成低k含氟和含碳氧化硅介电材料的方法，所述硅烷包括一种或多种有机氟硅烷，所述有机氟硅烷选自：（a）含有两个硅原子的有机氟硅烷连接 一个氧原子; （b）含有一个或多个碳原子连接的两个硅原子的有机氟硅烷，其中一个或多个碳原子各自键合到一个或多个氟原子，或一个或多个有机氟部分，或其组合; 和（c）含有与氧原子键合的硅原子的有机氟硅烷。 本发明还提供了通过与氧化剂反应形成低k含氟和含碳氧化硅电介质材料的方法，所述方法包括一种或多种包含一种或多种以Si-O键存在为特征的有机氟硅烷的硅烷。

公开(公告)号：US06743474B1

公开(公告)日：2004-06-01

申请号：US10035501

申请日：2001-10-25

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov ,  Richard Schinella

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov ,  Richard Schinella

IPC: C23C1600

CPC classification number: C23C16/45525 ,  C23C16/455 ,  C23C16/45527 ,  C23C16/463 ,  H01L21/3141 ,  Y10T428/265

Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.

Abstract translation: 提供了一种在衬底上形成层的方法。 通常，在衬底上沉积一层第一反应性物质。 第一反应性物质的层与第二反应性物质反应以产生第一产物。 未反应的反应物质优先解吸，留下第一产物的一层。

公开(公告)号：US6117749A

公开(公告)日：2000-09-12

申请号：US668365

申请日：1991-03-13

Applicant: Sheldon Aronowitz ,  Kranti Anand, deceased

Inventor： Sheldon Aronowitz ,  Kranti Anand, deceased

IPC: H01L29/06 ,  H01L21/28 ,  H01L21/3115 ,  H01L21/316 ,  H01L21/324 ,  H01L29/51 ,  H01L29/78 ,  H01L21/31

CPC classification number: H01L21/28185 ,  H01L21/28211 ,  H01L21/31155 ,  H01L29/51 ,  H01L29/517 ,  Y10S148/003 ,  Y10S148/024 ,  Y10S148/06

Abstract: Reduction in the net charge at the interface of a dielectric and a semiconductor material is achieved by placing atomic species in the dielectric near the interface. Preferably, these species are selected from the group of alkaline earth metals. The presence of these atoms results in a redistribution of the electronic density near the interface. The placement of the atoms is effected by ion implantation followed by multiple annealing steps at alternating low and high temperatures.

Abstract translation: 在电介质和半导体材料的界面处的净电荷的减少是通过将界面上的电介质放置在电介质中来实现的。 优选地，这些物质选自碱土金属组。 这些原子的存在导致界面附近的电子密度的再分布。 原子的放置通过离子注入实现，然后在交替的低温和高温下进行多个退火步骤。

公开(公告)号：US6090651A

公开(公告)日：2000-07-18

申请号：US434340

申请日：1999-11-05

Applicant: Helmut Puchner ,  Sheldon Aronowitz ,  Gary K. Giust

Inventor： Helmut Puchner ,  Sheldon Aronowitz ,  Gary K. Giust

IPC: H01L21/8238

CPC classification number: H01L21/823842 ,  Y10S438/929

Abstract: A method of forming a supersaturated layer on a semiconductor device, where an initial phase layer is deposited on the semiconductor device. The initial phase layer has a solid phase dopant saturation level and a liquid phase dopant saturation level, where the liquid phase dopant saturation level is greater than the solid phase dopant saturation level. A concentration of a dopant is impregnated within the initial phase layers, where the concentration of the dopant is greater than the solid phase dopant saturation level and no more than about the liquid phase dopant saturation level. The initial phase layer is annealed, without appreciably heating the semiconductor device, using an amount of energy that is high enough to liquefy the initial phase layer over a melt duration. This dissolves the dopant in the liquefied initial phase layer. The amount of energy is low enough to not appreciably gasify or ablate the initial phase layer. The liquefied initial phase layer is cooled to freeze the dissolved dopant in a supersaturated, electrically activated concentration, thereby forming the supersaturated layer. An initial phase layer of either polysilicon or amorphous silicon may be deposited over a CMOS device. After laser annealing the initial phase layer with a melt duration of no more than about 100 nanoseconds, it is transformed into a doped polysilicon gate electrode that can be patterned and further processed.

Abstract translation: 在半导体器件上形成过饱和层的方法，其中初始相层沉积在半导体器件上。 初始相层具有固相掺杂剂饱和水平和液相掺杂剂饱和水平，其中液相掺杂剂饱和水平大于固相掺杂剂饱和水平。 掺杂剂的浓度浸渍在初始相层中，其中掺杂剂的浓度大于固相掺杂剂饱和水平并且不大于约液相掺杂剂饱和水平。 使用一定量的足够高的能量使熔融持续时间内的初始相层液化的能量，初始相层退火，而不明显地加热半导体器件。 这溶解了液化的初始相层中的掺杂剂。 能量的量足够低，不能明显地气化或消融初始相层。 液化的初始相层被冷却以使过溶化的掺杂剂以过饱和的电活化浓度冷冻，从而形成过饱和层。 多晶硅或非晶硅的初始相层可以沉积在CMOS器件上。 在熔融持续时间不超过约100纳秒的激光退火初始相层之后，将其转变成可被图案化并进一步处理的掺杂多晶硅栅电极。

公开(公告)号：US6060375A

公开(公告)日：2000-05-09

申请号：US690577

申请日：1996-07-31

Applicant: Jon Owyang ,  Sheldon Aronowitz ,  James P. Kimball

Inventor： Jon Owyang ,  Sheldon Aronowitz ,  James P. Kimball

IPC: H01L21/28 ,  H01L21/3213 ,  H01L21/3215 ,  H01L29/423 ,  H01L21/302 ,  H01L21/425

CPC classification number: H01L21/32155 ,  H01L21/28114 ,  H01L21/32137 ,  H01L29/42376

Abstract: A crystalline semiconductor gate electrode having a re-entrant geometry and a process for making same are disclosed. The novel gate electrode may be formed from a polysilicon layer on a substrate by first implanting a masked polysilicon layer with a neutral species, i.e., a species which will not introduce a dopant into the polysilicon, such as a Group IV element, e.g., silicon, or a Group VIII element, e.g., argon. The neutral species is implanted into the masked polysilicon layer at an angle to provide a tapered implanted region which undercuts one side of the length (long dimension) of the mask. The substrate may then be rotated 180.degree. and then again implanted to provide a tapered implanted region which undercuts the opposite side of the length of the mask. When gate electrodes with such re-entrant geometry are to be formed on a substrate with their long axes at right angles to one another, i.e., some lying along an X axis in the plane of the masked polysilicon layer on the substrate and others lying along a Y axis in the plane of the masked polysilicon layer on the substrate, the substrate may be rotated 90.degree., rather than 180.degree., between each implantation, and four implantations, rather than two, are performed. After the implantations, the implanted masked polysilicon layer is then subject to an etch, preferably an anisotropic etch, which will remove the unmasked implanted portions of the polysilicon layer, as well as the implanted regions beneath the mask, resulting in a gate electrode with re-entrant or tapered sidewalls, i.e., resembling an inverted trapezoid in cross-section.

Abstract translation: 公开了一种具有凹入几何结构的晶体半导体栅电极及其制造方法。 新颖的栅电极可以由衬底上的多晶硅层形成，首先将具有中性物质的掩模多晶硅层，即不会将掺杂剂引入到多晶硅中的物质，例如IV族元素，例如硅 ，或VIII族元素，例如氩气。 将中性物质以一定角度注入到掩模多晶硅层中，以提供切割掩模长度（长尺寸）的一侧的锥形注入区域。 然后可以将衬底旋转180°，然后再次植入以提供锥形植入区域，其切割掩模长度的相对侧。 当具有这样的复数几何形状的栅电极将以其长轴彼此成直角的方式形成在衬底上时，即一些沿着衬底上的被掩膜的多晶硅层的平面中的X轴位于其上， 在衬底上的掩模多晶硅层的平面中的Y轴，衬底可以在每次注入之间旋转90度而不是180度，并且执行四次注入而不是两次。 在注入后，植入的掩膜多晶硅层然后进行蚀刻，优选是各向异性蚀刻，其将去除多晶硅层的未屏蔽的注入部分以及掩模下面的注入区域，从而形成栅电极 入口或锥形侧壁，即横截面类似倒梯形。

公开(公告)号：US5756369A

公开(公告)日：1998-05-26

申请号：US678718

申请日：1996-07-11

Applicant: Sheldon Aronowitz ,  Nicholas Eib ,  Jon S. Owyang

Inventor： Sheldon Aronowitz ,  Nicholas Eib ,  Jon S. Owyang

IPC: H01L21/20 ,  H01L21/00 ,  H01L21/268 ,  H01L21/285 ,  H01L21/316 ,  H01L21/324 ,  H01L21/66 ,  H01L23/34 ,  G01R31/26

CPC classification number: B24B37/013 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28518 ,  H01L21/31662 ,  H01L21/324 ,  H01L21/67115 ,  H01L22/26 ,  H01L23/34 ,  H01L2924/0002 ,  Y10S148/093 ,  Y10S148/094 ,  Y10S148/095

Abstract: Rapid Thermal Processing of a semiconductor wafer is performed by scanning a laser beam across a silicon dioxide film in contact with a surface of the wafer. The silicon dioxide film absorbs the energy from the laser beam and converts the energy to heat. The heat, in turn, is transferred to the wafer. Temperature feedback can be obtained to increase control and uniformity of temperatures across the wafer.

Abstract translation: 通过扫描与晶片表面接触的二氧化硅膜的激光束来进行半导体晶片的快速热处理。 二氧化硅膜吸收激光束的能量并将能量转换成热量。 热又转移到晶片上。 可以获得温度反馈以增加跨晶片温度的控制和均匀性。

公开(公告)号：US5739580A

公开(公告)日：1998-04-14

申请号：US788403

申请日：1997-01-27

Applicant: Sheldon Aronowitz ,  James Kimball

Inventor： Sheldon Aronowitz ,  James Kimball

IPC: H01L21/265 ,  H01L21/316 ,  H01L21/762 ,  H01L23/58 ,  H01L29/00

CPC classification number: H01L21/02238 ,  H01L21/02255 ,  H01L21/02299 ,  H01L21/26506 ,  H01L21/31662 ,  H01L21/76213 ,  Y10S438/911

Abstract: A process and resulting product is described for forming an oxide in a semiconductor substrate which comprises initially implanting the substrate with atoms of a noble gas, then oxidizing the implanted substrate at a reduced temperature, e.g., less than 900.degree. C., to form oxide in the implanted region of the substrate, and then etching the oxidized substrate to remove a portion of the oxide. The resulting oxidation produces a dual layer of oxide in the substrate. The upper layer is an extremely porous and frothy layer of oxide, while the lower layer is a more dense oxide. The upper porous layer of oxide can be selectively removed from the substrate by a mild etch, leaving the more dense oxide layer in the substrate. Further oxide can then be formed adjacent the dense layer of oxide in the substrate, either by oxide deposition over the dense oxide or by growing further oxide beneath the dense oxide layer. The initial oxide formed by the process appears to be temperature independent, at temperatures of 900.degree. C. or less, with oxide formation apparently dependent upon the extent of the implanted regions of the substrate, rather than upon temperature, resulting in thermal savings. Furthermore, the excess implanted noble gas in the substrate adjacent the oxide formed therein can have beneficial effects in inhibiting the formation of parasitic field transistors and in greater control over field thresholds.

Abstract translation: 描述了一种工艺和产生的产品，用于在半导体衬底中形成氧化物，其包括首先用惰性气体原子注入衬底，然后在降低的温度例如低于900℃下氧化注入的衬底，以形成氧化物 在衬底的注入区域中，然后蚀刻氧化的衬底以除去氧化物的一部分。 所产生的氧化物在衬底中产生双层氧化物。 上层是氧化物极其多孔和泡沫层，而下层是更致密的氧化物。 氧化物的上部多孔层可以通过温和的蚀刻从衬底中选择性地去除，从而在衬底中留下更致密的氧化物层。 然后可以通过在致密氧化物上的氧化物沉积或通过在致密氧化物层下生长另外的氧化物在衬底中的致密氧化物层附近形成氧化物。 通过该方法形成的初始氧化物在900℃或更低的温度下似乎与温度无关，氧化物形成显然取决于衬底的注入区域的程度，而不是温度，导致热量节省。 此外，与其中形成的氧化物相邻的衬底中的过量注入的惰性气体可以在抑制寄生场晶体管的形成和对场阈值的更大控制方面具有有益的效果。