公开(公告)号：US20050281090A1

公开(公告)日：2005-12-22

申请号：US11152033

申请日：2005-06-14

Applicant: Cyrille Dray ,  Sebastien Barasinski ,  Jean Lasseuguette ,  Christophe Frey ,  Richard Fournel

Inventor： Cyrille Dray ,  Sebastien Barasinski ,  Jean Lasseuguette ,  Christophe Frey ,  Richard Fournel

IPC: G11C7/18 ,  G11C8/10 ,  G11C11/16 ,  G11C16/04

CPC classification number: G11C11/16

Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Abstract translation: 存储器件包括由至少一个写入段形成的至少一个分段写入线。 编程电路由存储器件的写入模式中的行地址电路控制，以对耦合到分段写入线的至少一个存储单元进行编程。 读取位线连接到用于在存储器件的读取模式下读取单元的内容的读取电路。 读取位线以写入模式与线路地址电路协作，以控制分段写入线的编程电路。

公开(公告)号：US06707697B2

公开(公告)日：2004-03-16

申请号：US10126442

申请日：2002-04-19

Applicant: Cyrille Dray ,  Richard Fournel

Inventor： Cyrille Dray ,  Richard Fournel

IPC: G11C1700

CPC classification number: G11C16/0433 ,  H01L27/115

Abstract: An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.

Abstract translation: FAMOS存储器包括存储器单元，其中每个存储单元包括绝缘栅极晶体管，以及具有连接到绝缘栅极晶体管的源极的漏极的第一存取晶体管。 FAMOS存储器还包括绝缘晶体管，其具有分别连接到同一行的两个相邻单元的绝缘栅极晶体管的源极的漏极和源极。 每个绝缘栅极晶体管具有环形结构，并且梯形分离区域使得同一行的单元绝缘。

公开(公告)号：US09230636B2

公开(公告)日：2016-01-05

申请号：US14137808

申请日：2013-12-20

Applicant: Pascal A. Meinerzhagen ,  Jaydeep P. Kulkarni ,  Muhammad M. Khellah ,  Cyrille Dray ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

Inventor： Pascal A. Meinerzhagen ,  Jaydeep P. Kulkarni ,  Muhammad M. Khellah ,  Cyrille Dray ,  Dinesh Somasekhar ,  James W. Tschanz ,  Vivek K. De

IPC: G11C5/14 ,  G11C11/4074 ,  G11C11/16 ,  G11C16/06 ,  G11C11/406 ,  G11C11/4076 ,  G11C5/06 ,  G11C11/408

CPC classification number: G11C11/4074 ,  G11C5/063 ,  G11C5/14 ,  G11C5/145 ,  G11C5/148 ,  G11C11/1697 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4085 ,  G11C11/4087 ,  G11C11/417 ,  G11C16/06

Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.

Abstract translation: 描述了一种装置，包括：提供第一电源的第一电源节点，第二电源节点和第三电源节点; 第一晶体管，其可操作以耦合所述第一和第二电源节点; 以及电荷泵电路，以一种模式向第三电源节点提供升压电压，并且在另一模式下从第二功率节点恢复电荷。 描述了一种存储单元，其包括：可操作以刷新的DRAM; 门极电源节点，其耦合到DRAM以向DRAM提供门控电源; 以及充电回收电路，用于在DRAM被刷新之后从门控电源节点恢复电荷。

公开(公告)号：US20140153313A1

公开(公告)日：2014-06-05

申请号：US13689869

申请日：2012-11-30

Applicant: El Mehdi Boujamaa ,  Cyrille Dray

Inventor： El Mehdi Boujamaa ,  Cyrille Dray

IPC: G11C7/06 ,  G11C11/21

CPC classification number: G11C11/16 ,  G11C7/062 ,  G11C7/14 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/004 ,  G11C27/02 ,  G11C2013/0054

Abstract: A sense amplifier system includes a first path, a second path, a memory cell, a first reference cell, a second reference cell, and a switch component. The switch component is configured to switch connections between the first and second reference cells and the first and second paths according to a sampling phase and an amplification phase.

Abstract translation: 感测放大器系统包括第一路径，第二路径，存储器单元，第一参考单元，第二参考单元和开关组件。 开关组件被配置为根据采样相位和放大阶段来切换第一和第二参考单元与第一和第二路径之间的连接。

公开(公告)号：US20120099359A1

公开(公告)日：2012-04-26

申请号：US12911603

申请日：2010-10-25

Applicant: Cyrille Dray ,  Alexander Ney ,  Karl Hofmann

Inventor： Cyrille Dray ,  Alexander Ney ,  Karl Hofmann

IPC: G11C5/06

CPC classification number: G11C11/1659 ,  G11C8/08 ,  G11C13/0002 ,  G11C13/0028 ,  G11C13/003 ,  G11C17/12 ,  G11C2213/74 ,  G11C2213/79

Abstract: Representative implementations of memory devices have transistors between memory cells of a memory device. Memory devices may be arranged in memory arrays. The use of transistors may include alternately providing electrical isolation or current paths between pairs or groups of memory cells in a memory array.

Abstract translation: 存储器件的代表性实现在存储器件的存储器单元之间具有晶体管。 存储器件可以被布置在存储器阵列中。 晶体管的使用可以包括交替地在存储器阵列中的存储器单元的对或组之间提供电隔离或电流路径。

公开(公告)号：US07782093B2

公开(公告)日：2010-08-24

申请号：US11805305

申请日：2007-05-23

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: H03K5/22

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1534

Abstract: The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the output node. The edge transition detector includes a logic device with a first input coupled to the input node and an output coupled to a control terminal of the switch to enable the switch to conduct, thereby effecting a transition of the output signal from a first logic level to a second logic level in response to the input signal. A feedback path is provided from the output node to a second input of the logic device to disable switch conductivity when the output signal completes the logic transition from the first logic level to the second logic level.

Abstract translation: 本发明涉及一种边缘转换检测器，以及一种操作边缘转换检测器的方法。 集成电路包括用于响应于输入信号在输出节点产生输出信号的边沿转换检测器。 边缘转换检测器包括耦合到输出节点的开关。 边缘跃迁检测器包括具有耦合到输入节点的第一输入和耦合到开关的控制端的输出的逻辑器件，以使开关能导通，从而实现输出信号从第一逻辑电平到 响应于输入信号的第二逻辑电平。 当输出信号完成从第一逻辑电平到第二逻辑电平的逻辑转换时，反馈路径从输出节点提供给逻辑器件的第二输入，以禁止开关电导率。

公开(公告)号：US07630264B2

公开(公告)日：2009-12-08

申请号：US11782418

申请日：2007-07-24

Applicant: Cyrille Dray ,  Stephany Bouniol ,  Magali Hage Hassan ,  Luc Palau

Inventor： Cyrille Dray ,  Stephany Bouniol ,  Magali Hage Hassan ,  Luc Palau

IPC: G11C7/02

CPC classification number: G11C29/50 ,  G11C11/41 ,  G11C29/24 ,  G11C29/50012

Abstract: An apparatus including a memory cell, a reference cell, a control unit, coupled to the memory cell and the reference cell, and configured to initiate write processes of the memory cell and the reference cell, and a detection unit, coupled to the reference cell, and configured to detect a write completion of the reference cell. Related methods are also disclosed.

Abstract translation: 一种装置，包括耦合到存储单元和参考单元的存储单元，参考单元，控制单元，并且被配置为启动存储单元和参考单元的写入处理;以及检测单元，耦合到参考单元 并且被配置为检测参考单元的写入完成。 还公开了相关方法。

公开(公告)号：US07545686B2

公开(公告)日：2009-06-09

申请号：US11083112

申请日：2005-03-17

Applicant: Jean Lasseuguette ,  Cyrille Dray ,  Sébastien Barasinski

Inventor： Jean Lasseuguette ,  Cyrille Dray ,  Sébastien Barasinski

IPC: G11C7/00 ,  G11C7/22

CPC classification number: G11C11/16 ,  G11C5/147 ,  H03F1/223 ,  H03F3/45188 ,  H03F2203/45248

Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.

Abstract translation: 本发明涉及一种用于在MRAM型集成电路存储器中的至少一个写入导线上建立写入电流的装置，该器件包括电流镜，该电流镜由作为参考调节共源共栅级的第一级构成，该级用于接收全部或部分写入 其输入电流和作为复制调制共源共栅级的第二级将写入电流复制到写入线上。

公开(公告)号：US07489559B2

公开(公告)日：2009-02-10

申请号：US11643009

申请日：2006-12-19

Applicant: Cyrille Dray ,  Stéphane Gamet

Inventor： Cyrille Dray ,  Stéphane Gamet

IPC: G11C11/34

CPC classification number: H03K17/102 ,  H03K17/693

Abstract: An embodiment of the invention pertains to an nth order selector switch device comprising: a first arm comprising n transistors series-connected between a first input to which a 0-ranking potential is applied, and an output; and a second arm comprising n transistors series-connected between a second input to which a 0-ranking potential is applied, and the output. The device according to the invention also comprises: a means to produce n−1 potentials ranked 1 to n−1 included between the potential ranked 0 and the potential ranked n; and a driving means for the production, from the n+1 potentials ranked 0 to n, of control signals suited to driving the gates of the transistors of the first arm and the gates of the transistors of the second arm so that the transistors of one of the arms are on and the transistors of the other arm are off depending on the value of the n-ranking potential relative to the value of the 0-ranking potential.

Abstract translation: 本发明的实施例涉及一种第n级选择器开关装置，包括：第一臂，包括串联连接在施加0级电位的第一输入端和输出端之间的n个晶体管; 以及第二臂，包括串联连接在施加0级电位的第二输入和输出之间的n个晶体管。 根据本发明的装置还包括：产生潜在排名0和潜在等级为n之间的包括1至n-1的n-1个电位的装置; 以及用于从适于驱动第一臂的晶体管的栅极和第二臂的晶体管的栅极的控制信号产生从0到n的n + 1个电位的驱动装置，使得一个晶体管 根据相对于0级电位值的n级势的值，另一臂的晶体管截止。

公开(公告)号：US20080159014A1

公开(公告)日：2008-07-03

申请号：US11617336

申请日：2006-12-28

Applicant: Cyrille Dray ,  Francois Jacquet

Inventor： Cyrille Dray ,  Francois Jacquet

IPC: G11C5/14

CPC classification number: G11C11/413

Abstract: The invention relates to a device, and also to a corresponding method of implementation, for SRAM memory information storage, powered by a voltage VDD and comprising: an array of base cells organised in base columns, and at least one mirror column of mirror cells, liable to simulate the behaviour of the cells in a base column, The invention is characterised in that the device further comprises: Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying the mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 本发明涉及一种由电压VDD供电的SRAM存储器信息存储器的器件以及相应的实现方法，包括：组合在基本列中的基本单元阵列，以及镜像单元的至少一个反射镜列， 本发明的特征在于，该装置还包括：在反射镜列中的仿真装置，其是基极柱中最大限制电池的装置，用于改变反射镜电源电压的装置 （VDDMMOCK），以及用于复制仿真基列中的反射镜电源电压的装置。