STRUCTURE AND METHOD TO CONTROL OXIDATION IN HIGH-K GATE STRUCTURES
    33.
    发明申请
    STRUCTURE AND METHOD TO CONTROL OXIDATION IN HIGH-K GATE STRUCTURES 有权
    控制高K门结构氧化的结构和方法

    公开(公告)号:US20090243031A1

    公开(公告)日:2009-10-01

    申请号:US12055682

    申请日:2008-03-26

    IPC分类号: H01L29/49 H01L21/441

    摘要: In one embodiment, the present invention provides a method of fabricating a semiconducting device that includes providing a substrate including at least one semiconducting region and at least one oxygen source region; forming an oxygen barrier material atop portions of an upper surface of the at least one oxygen region; forming a high-k gate dielectric on the substrate including the at least one semiconducting region, wherein oxygen barrier material separates the high-k gate dielectric from the at least one oxygen source material; and forming a gate conductor atop the high-k gate dielectric.

    摘要翻译: 在一个实施例中,本发明提供一种制造半导体器件的方法,其包括提供包括至少一个半导体区域和至少一个氧源区域的衬底; 在所述至少一个氧区的上表面的部分顶部形成氧阻隔材料; 在包括所述至少一个半导体区域的衬底上形成高k栅极电介质,其中氧阻挡材料将所述高k栅极电介质与所述至少一个氧源材料分离; 并在高k栅极电介质的顶部形成栅极导体。

    Manufacturing of cavity fuses on gate conductor level
    39.
    发明授权
    Manufacturing of cavity fuses on gate conductor level 失效
    在栅极导体级制造腔体保险丝

    公开(公告)号:US06274440B1

    公开(公告)日:2001-08-14

    申请号:US09282134

    申请日:1999-03-31

    IPC分类号: H01L21336

    摘要: A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.

    摘要翻译: 用于在栅极导体堆叠上形成腔体熔断器的结构和方法。 该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底,在栅极导体堆叠周围形成衬底周围的氧化物层,蚀刻通过氧化物层到衬底的电接触孔, 第一导电材料以与栅极导体堆叠建立电接触,蚀刻氧化物层的最上面的氧化物层中的图案,在氧化物层和电触点上沉积第二导电材料的导电层,平坦化导电层,由此 导电材料仅保留在图案中,各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔,并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层, 形成在导电层图案的至少一部分之下,g 包括保险丝的导体堆叠。

    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure
    40.
    发明授权
    Method of eliminating a critical mask using a blockout mask and a resulting semiconductor structure 失效
    使用阻挡掩模和所得半导体结构消除临界掩模的方法

    公开(公告)号:US06232222B1

    公开(公告)日:2001-05-15

    申请号:US09395418

    申请日:1999-09-14

    IPC分类号: H01L214763

    摘要: A method of forming a semiconductor structure may include forming a semiconductor substrate having an array region and a support region, forming a semiconductor substrate and a gate stack over the support region of the substrate and applying a critical mask over the support region and the array region. The critical mask may have a first opening at an area corresponding to the array region and a second opening at an area corresponding to the support region. Contact holes may be formed in a glass layer at areas corresponding to the first and second opening. After removing the critical mask, a first blockout mask may be applied over the array region and a first conductive type dopant may be added to exposed polysilicon corresponding to openings of the blockout mask or gate contacts may be formed.

    摘要翻译: 形成半导体结构的方法可以包括形成具有阵列区域和支撑区域的半导体衬底,在衬底的支撑区域上形成半导体衬底和栅叠层,并在衬底区域和阵列区域上施加临界掩模 。 临界掩模可以在对应于阵列区域的区域处具有第一开口,并且在对应于支撑区域的区域处具有第二开口。 可以在对应于第一和第二开口的区域的玻璃层中形成接触孔。 在去除临界掩模之后,可以在阵列区域上施加第一堵塞掩模,并且可以形成第一导电型掺杂剂,以对应于封闭掩模的开口或栅极触点形成对应于暴露的多晶硅。