公开(公告)号：US08912424B2

公开(公告)日：2014-12-16

申请号：US13612632

申请日：2012-09-12

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Bahman Hekmatshoar-Tabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Bahman Hekmatshoar-Tabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC分类号： H01L21/00

CPC分类号： H01L31/1892 ,  H01L31/02167 ,  H01L31/0687 ,  H01L31/0725 ,  H01L31/0747 ,  H01L31/076 ,  H01L31/1808 ,  H01L31/1812 ,  Y02E10/544 ,  Y02E10/548 ,  Y02P70/521

摘要： A method of forming a photovoltaic device that includes bonding a substrate to a germanium-containing semiconductor layer with a stressor layer, wherein the stressor layer cleaves the germanium-containing semiconductor layer. At least one semiconductor layer is formed on a cleaved surface of the germanium-containing semiconductor layer that is opposite the conductivity type of the germanium-containing semiconductor layer to provide a first solar cell. The first solar cell absorbs a first range of wavelengths. At least one second solar cell may be formed on the first solar cell, wherein the at least one second solar cell is composed of at least one semiconductor material to absorb a second range of wavelengths that is different than the first range wavelengths absorbed by the first solar cell.

摘要翻译： 一种形成光伏器件的方法，该光电器件包括将衬底粘合到含锗半导体层与应力层，其中所述应力层切割含锗半导体层。 在与含锗半导体层的导电类型相反的含锗半导体层的切割表面上形成至少一个半导体层以提供第一太阳能电池。 第一太阳能电池吸收第一波长范围。 可以在第一太阳能电池上形成至少一个第二太阳能电池，其中至少一个第二太阳能电池由至少一个半导体材料组成，以吸收不同于由第一太阳能电池吸收的第一范围波长的第二波长范围 太阳能电池。

公开(公告)号：US20140034699A1

公开(公告)日：2014-02-06

申请号：US13565378

申请日：2012-08-02

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ibrahim Alhomoudi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Ning Li ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ibrahim Alhomoudi

IPC分类号： B26F3/00

CPC分类号： H01L21/304 ,  B26F3/00 ,  C30B33/00 ,  C30B33/06 ,  H01L21/2855 ,  H01L21/32051 ,  H01L21/321 ,  H01L31/1892 ,  Y02E10/50 ,  Y10T225/10

摘要： Methods for removing a material layer from a base substrate utilizing spalling in which mode III stress, i.e., the stress that is perpendicular to the fracture front created in the base substrate, during spalling is reduced. The substantial reduction of the mode III stress during spalling results in a spalling process in which the spalled material has less surface roughness at one of its' edges as compared to prior art spalling processes in which the mode III stress is present and competes with spalling.

摘要翻译： 利用剥落的材料层从基底基板上去除材料层的方法，其中在剥离期间模式III应力即垂直于在基底基板中产生的断裂面的应力减小。 在剥落过程中模式III应力的显着降低导致剥落过程，其中剥离材料在其一个边缘处具有较小的表面粗糙度，与现有技术的剥离过程相比，其中存在模式III应力并与剥落相竞争。

公开(公告)号：US20130005116A1

公开(公告)日：2013-01-03

申请号：US13172793

申请日：2011-06-29

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi ,  Norma E. Sosa Cortes

IPC分类号： H01L21/301

CPC分类号： H01L21/304 ,  C03C15/00 ,  C03C2218/34 ,  H01L31/1892

摘要： A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region where the stressor layer is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In one embodiment, the method includes forming an edge exclusion material on an upper surface and near an edge of a base substrate. A stressor layer is then formed on exposed portions of the upper surface of the base substrate and atop the edge exclusion material, A portion of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled.

摘要翻译： 使用边缘排除区域（其中应力层不存在（在沉积期间排除或随后除去）或存在但显着不附着于排除区域中的基底表面的边缘排除区域来最小化边缘相关底物断裂的方法 被提供。 在一个实施例中，该方法包括在基底基板的上表面和边缘附近形成边缘排除材料。 然后在基底基板的上表面和边缘排除材料的顶部的暴露部分上形成应力层，然后剥离位于应力层下方并且不被边缘排除材料覆盖的基底基板的一部分 。

公开(公告)号：US20120322230A1

公开(公告)日：2012-12-20

申请号：US13159877

申请日：2011-06-14

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Paul A. Lauro ,  Devendra K. Sadana ,  Davood Shahrjerdi

IPC分类号： H01L21/78

CPC分类号： H01L21/7813 ,  H01L21/304

摘要： The present disclosure provides a method for forming two device wafers starting from a single base substrate. The method includes first providing a structure which includes a base substrate with device layers located on, or within, a topmost surface and a bottommost surface of the base substrate. The base substrate may have double side polished surfaces. The structure including the device layers is spalled in a region within the base substrate that is between the device layers. The spalling provides a first device wafer including a portion of the base substrate and one of the device layers, and a second device wafer including another portion of the base substrate and the other of the device layer.

摘要翻译： 本公开提供了从单个基底基板开始形成两个器件晶片的方法。 该方法包括首先提供一种结构，该结构包括具有位于基底板的最上表面和最底表面之上或之内的器件层的基底基板。 基底可以具有双面抛光表面。 包括器件层的结构在基底衬底内位于器件层之间的区域中被剥落。 剥落提供了包括基底部分的一部分和器件层之一的第一器件晶片，以及包括基底衬底的另一部分和器件层另一部分的第二器件晶片。

公开(公告)号：US20120305940A1

公开(公告)日：2012-12-06

申请号：US13151238

申请日：2011-06-01

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Bruce B. Doris ,  Lisa F. Edge ,  Keith E. Fogel ,  Johnathan E. Faltermeier ,  Jinghong Li ,  Alexander Reznicek ,  Devendra K. Sadana ,  Bin Yang

IPC分类号： H01L29/24 ,  H01L21/20

CPC分类号： H01L21/02529 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/78654

摘要： A method and structure are disclosed for a defect free Si:C source/drain in an NFET device. A wafer is accepted with a primary surface of {100} crystallographic orientation. A recess is formed in the wafer in such manner that the bottom surface and the four sidewall surfaces of the recess are all having {100} crystallographic orientations. A Si:C material is eptaxially grown in the recess, and due to the crystallographic orientations the defect density next to each of the four sidewall surfaces is essentially the same as next to the bottom surface. The epitaxially filled recess is used in the source/drain fabrication of an NFET device. The NFET device is oriented along the crystallographic direction, and has the device channel under a tensile strain due to the defect free Si:C in the source/drain.

摘要翻译： 公开了在NFET器件中的无缺陷Si：C源极/漏极的方法和结构。 接受具有{100}晶体取向的主表面的晶片。 以这样的方式在晶片中形成凹部，使得凹部的底表面和四个侧壁表面都具有{100}晶体取向。 Si：C材料在凹槽中被轴向生长，并且由于晶体取向，邻近四个侧壁表面的缺陷密度基本上与下表面相同。 外延填充的凹槽用于NFET器件的源极/漏极制造。 NFET器件沿着<100>结晶方向取向，由于源极/漏极中的缺陷Si：C，器件沟道处于拉伸应变状态。

公开(公告)号：US07897444B2

公开(公告)日：2011-03-01

申请号：US12363239

申请日：2009-01-30

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L21/84

CPC分类号： H01L21/76243 ,  H01L29/66772 ,  H01L29/7849 ,  H01L29/78654

摘要： A strained (tensile or compressive) semiconductor-on-insulator material is provided in which a single semiconductor wafer and a separation by ion implantation of oxygen process are used. The separation by ion implantation of oxygen process, which includes oxygen ion implantation and annealing creates, a buried oxide layer within the material that is located beneath the strained semiconductor layer. In some embodiments, a graded semiconductor buffer layer is located beneath the buried oxide layer, while in other a doped semiconductor layer including Si doped with at least one of B or C is located beneath the buried oxide layer.

摘要翻译： 提供了一种应变（拉伸或压缩）半导体绝缘体材料，其中使用单个半导体晶片和通过氧气工艺的离子注入分离。 通过离子注入氧气工艺的分离，其中包括氧离子注入和退火，产生位于应变半导体层之下的材料内的掩埋氧化物层。 在一些实施例中，渐变半导体缓冲层位于掩埋氧化物层的下方，而在其它掺杂半导体层中，包含掺杂有B或C中的至少一个的掺杂半导体层位于掩埋氧化物层的下方。

公开(公告)号：US20100221867A1

公开(公告)日：2010-09-02

申请号：US12436249

申请日：2009-05-06

申请人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Harold J. Hovel ,  Daniel A. Inns ,  Jeehwan Kim ,  Devendra K. Sadana ,  Katherine L. Saenger ,  Ghavam G. Shahidi

IPC分类号： H01L31/0376 ,  H01L21/762

CPC分类号： H01L31/03921 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/02667 ,  H01L21/7624 ,  H01L21/76245 ,  H01L21/76262 ,  H01L31/046 ,  H01L31/0463 ,  H01L31/0465 ,  H01L31/1872 ,  Y02E10/50 ,  Y02P70/521

摘要： A lost cost method for fabricating SOI substrates is provided. The method includes forming a stack of p-type doped amorphous Si-containing layers on a semiconductor region of a substrate by utilizing an evaporation deposition process. A solid phase recrystallization step is then performed to convert the amorphous Si-containing layers within the stack into a stack of p-type doped single crystalline Si-containing layers. After recrystallization, the single crystalline Si-containing layers are subjected to anodization and at least an oxidation step to form an SOI substrate. Solar cells and/or other semiconductor devices can be formed on the upper surface of the inventive SOI substrate.

摘要翻译： 提供了一种用于制造SOI衬底的损耗成本方法。 该方法包括通过利用蒸发沉积工艺在衬底的半导体区域上形成一层p型掺杂的非晶态含Si层。 然后进行固相重结晶步骤，以将叠层内的非晶态含硅层转化为p型掺杂单晶含Si层的堆叠。 重结晶后，对单晶含Si层进行阳极氧化和至少氧化步骤以形成SOI衬底。 太阳能电池和/或其他半导体器件可以形成在本发明的SOI衬底的上表面上。

公开(公告)号：US20100032684A1

公开(公告)日：2010-02-11

申请号：US12539248

申请日：2009-08-11

申请人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Huajie Chen ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L29/267 ,  H01L29/161 ,  H01L29/165

CPC分类号： H01L21/26506 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/2658

摘要： A method for fabricating substantially relaxed SiGe alloy layers with a reduced planar defect density is disclosed The method of the present invention includes forming a strained Ge-containing layer on a surface of a Si-containing substrate; implanting ions at or below the Ge-containing layer/Si-containing substrate interface and heating to form a substantially relaxed SiGe alloy layer that has a reduced planar defect density. A substantially relaxed SiGe-on-insulator substrate material having a SiGe layer with a reduced planar defect density as well as heterostructures containing the same are also provided.

摘要翻译： 公开了一种制造具有减小的平面缺陷密度的基本上松弛的SiGe合金层的方法。本发明的方法包括在含Si衬底的表面上形成应变的含Ge层; 在含锗层/含Si衬底界面处或下方注入离子，并加热以形成具有减小的平面缺陷密度的基本上松弛的SiGe合金层。 还提供了具有具有减小的平面缺陷密度的SiGe层以及含有该SiGe层的异质结构的基本上松弛的绝缘体上硅衬底材料。

公开(公告)号：US07592671B2

公开(公告)日：2009-09-22

申请号：US11620663

申请日：2007-01-06

申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam Shahidi

IPC分类号： H01L29/94

CPC分类号： H01L21/76259 ,  Y10S438/967

摘要： A cost efficient and manufacturable method of fabricating strained semiconductor-on-insulator (SSOI) substrates is provided that avoids wafer bonding. The method includes growing various epitaxial semiconductor layers on a substrate, wherein at least one of the semiconductor layers is a doped and relaxed semiconductor layer underneath a strained semiconductor layer; converting the doped and relaxed semiconductor layer into a porous semiconductor via an electrolytic anodization process, and oxidizing to convert the porous semiconductor layer into a buried oxide layer. The method provides a SSOI substrate that includes a relaxed semiconductor layer on a substrate; a high-quality buried oxide layer on the relaxed semiconductor layer; and a strained semiconductor layer on the high-quality buried oxide layer. In accordance with the present invention, the relaxed semiconductor layer and the strained semiconductor layer have identical crystallographic orientations.

摘要翻译： 提供了制造应变半导体绝缘体（SSOI）衬底的成本有效和可制造的方法，其避免晶片接合。 该方法包括在衬底上生长各种外延半导体层，其中半导体层中的至少一个是在应变半导体层下面的掺杂和弛豫半导体层; 通过电解阳极氧化处理将掺杂和松弛的半导体层转化成多孔半导体，并氧化以将多孔半导体层转化为掩埋氧化物层。 该方法提供了在衬底上包括松弛半导体层的SSOI衬底; 在松弛的半导体层上形成高质量的掩埋氧化物层; 以及在高质量掩埋氧化物层上的应变半导体层。 根据本发明，松弛半导体层和应变半导体层具有相同的晶体取向。

公开(公告)号：US07501318B2

公开(公告)日：2009-03-10

申请号：US10984212

申请日：2004-11-09

申请人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi

发明人： Stephen W. Bedell ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi

IPC分类号： H01L21/84

CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implant rich region in the Si-containing substrate. The implant rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

摘要翻译： 提供了使用SIMOX和Ge相互扩散形成基本上松弛的，优质的绝缘体上硅衬底材料的方法。 该方法包括首先将离子注入到含Si衬底中以在含Si衬底中形成富含注入区的区域。 注入富含区域具有足够的离子浓度，使得在随后的高温退火期间，形成耐Ge扩散的阻挡层。 接下来，在含Si衬底的表面上形成Ge含有层，然后在允许形成阻挡层和Ge的相互扩散的温度下进行加热步骤，从而形成基本上松弛的单晶SiGe层 阻挡层顶部。