公开(公告)号：US20110140126A1

公开(公告)日：2011-06-16

申请号：US12773275

申请日：2010-05-04

Applicant: Stephen Joseph Gaul ,  Francois Hebert

Inventor： Stephen Joseph Gaul ,  Francois Hebert

IPC: H01L23/373 ,  H01L21/768 ,  H01L23/48 ,  H01L21/02

CPC classification number: H01L23/3732 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/06181 ,  H01L2224/06515 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/14 ,  H01L2924/00

Abstract: A semiconductor device assembly and method can include a single semiconductor layer or stacked semiconductor layers, for example semiconductor wafers or wafer sections (semiconductor dice). On each semiconductor layer, a diamond layer formed therethrough can aid in the routing and dissipation of heat. The diamond layer can include a first portion on the back of the semiconductor layer, and one or more second portions which extend vertically into the semiconductor layer, for example completely through the semiconductor layer. Thermal contact can then be made to the diamond layer to conduct heat away from the one or more semiconductor layers. A conductive via can be formed through the diamond layers to provide signal routing and heat dissipation capabilities.

Abstract translation: 半导体器件组件和方法可以包括单个半导体层或层叠的半导体层，例如半导体晶片或晶片部分（半导体晶片）。 在每个半导体层上，通过其形成的金刚石层可有助于散热和散热。 金刚石层可以包括半导体层背面的第一部分和垂直延伸到半导体层中的一个或多个第二部分，例如完全穿过半导体层。 然后可以对金刚石层进行热接触以将热量从一个或多个半导体层导出。 可以通过金刚石层形成导电通孔，以提供信号路由和散热能力。

公开(公告)号：US20110121808A1

公开(公告)日：2011-05-26

申请号：US12796178

申请日：2010-06-08

Applicant: Dev Alok Girdhar ,  Francois Hebert

Inventor： Dev Alok Girdhar ,  Francois Hebert

IPC: G05F3/02 ,  H01L21/8234

CPC classification number: H01L27/088

Abstract: A voltage converter includes an output circuit having a high side device and a low side device which can be formed on a single die (i.e. a “PowerDie”) and connected to each other through a semiconductor substrate. Both the high side device and the low side device can include lateral diffused metal oxide semiconductor (LDMOS) transistors. Because both output transistors include the same type of transistors, the two devices can be formed simultaneously, thereby reducing the number of photomasks over other voltage converter designs. The voltage converter can further include a controller circuit on a different die which can be electrically coupled to, and co-packaged with, the PowerDie.

Abstract translation: 电压转换器包括具有高侧器件的输出电路和可以形成在单个管芯（即“PowerDie”）上并通过半导体衬底相互连接的低侧器件。 高侧器件和低侧器件都可以包括横向扩散的金属氧化物半导体（LDMOS）晶体管。 因为两个输出晶体管都包含相同类型的晶体管，所以可以同时形成两个器件，从而减少超过其它电压转换器设计的光掩模数量。 电压转换器还可以包括在不同的管芯上的控制器电路，其可以与PowerDie电耦合并与其一体化。

公开(公告)号：US20100330754A1

公开(公告)日：2010-12-30

申请号：US12823060

申请日：2010-06-24

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L21/335

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

Abstract: Various embodiments of the disclosure include the formation of enhancement-mode (e-mode) gate injection high electron mobility transistors (HEMT). Embodiments can include GaN, AlGaN, and InAlN based HEMTs. Embodiments also can include self-aligned P-type gate and field plate structures. The gates can be self-aligned to the source and drain, which can allow for precise control over the gate-source and gate-drain spacing. Additional embodiments include the addition of a GaN cap structure, an AlGaN buffer layer, AlN, recess etching, and/or using a thin oxidized AlN layer. In manufacturing the HEMTs according to present teachings, selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) can both be utilized to form gates.

Abstract translation: 本公开的各种实施例包括形成增强型（e模式）栅极注入高电子迁移率晶体管（HEMT）。 实施例可以包括GaN，AlGaN和基于InAlN的HEMT。 实施例还可以包括自对准P型门和场板结构。 栅极可以与源极和漏极自对准，这可以精确控制栅极源极和栅极 - 漏极间隔。 另外的实施例包括添加GaN帽结构，AlGaN缓冲层，AlN，凹陷蚀刻和/或使用薄的氧化AlN层。 在根据本教导制造HEMT时，可以利用选择性外延生长（SEG）和外延横向过度生长（ELO）来形成栅极。

公开(公告)号：US20100237416A1

公开(公告)日：2010-09-23

申请号：US12406048

申请日：2009-03-17

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/66659 ,  H01L29/7835

Abstract: Lateral DMOS devices having improved drain contact structures and methods for making the devices are disclosed. A semiconductor device comprises a semiconductor substrate; an epitaxial layer on top of the substrate; a drift region at a top surface of the epitaxial layer; a source region at a top surface of the epitaxial layer; a channel region between the source and drift regions; a gate positioned over a gate dielectric on top of the channel region; and a drain contact trench that electrically connects the drift layer and substrate. The contact trench includes a trench formed vertically from the drift region, through the epitaxial layer to the substrate and filled with an electrically conductive drain plug; electrically insulating spacers along sidewalls of the trench; and an electrically conductive drain strap on top of the drain contact trench that electrically connects the drain contact trench to the drift region.

Abstract translation: 公开了具有改进的漏极接触结构的侧面DMOS器件和用于制造器件的方法。 半导体器件包括半导体衬底; 在衬底的顶部上的外延层; 位于外延层顶表面的漂移区; 在所述外延层的顶表面处的源极区; 源极和漂移区域之间的沟道区域; 栅极位于沟道区域顶部的栅极电介质上; 以及电连接漂移层和衬底的漏极接触沟槽。 接触沟槽包括从漂移区垂直形成的沟槽，穿过外延层到衬底并填充有导电排放塞; 沿沟槽侧壁的电绝缘垫片; 以及在漏极接触沟槽的顶部上的导电漏极带，其将漏极接触沟槽电连接到漂移区域。

公开(公告)号：US20100133670A1

公开(公告)日：2010-06-03

申请号：US12326065

申请日：2008-12-01

Applicant: Kai Liu ,  Francois Hebert ,  Lei Shi

Inventor： Kai Liu ,  Francois Hebert ,  Lei Shi

IPC: H01L23/495 ,  H01L21/60

CPC classification number: H01L21/56 ,  H01L21/50 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40249 ,  H01L2224/4103 ,  H01L2224/48247 ,  H01L2224/73263 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/37099

Abstract: A top-side cooled semiconductor package with stacked interconnection plate is disclosed. The semiconductor package includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.

Abstract translation: 公开了一种具有堆叠互连板的顶侧冷却半导体封装。 半导体封装包括具有端子引线的电路基板，电路基板顶部的半导体管芯，用于将半导体管芯的顶部接触区域与电路基板接合和互连的低热电阻紧密互连板，低热阻堆叠互连板 位于用于顶侧冷却的紧密互连板顶部，用于封装包装的模制密封剂，除了暴露堆叠的互连板的顶表面以保持有效的顶侧冷却。 堆叠的互连板的顶部可以包括在紧密互连板上方的周边突出部。 外围悬垂允许最大化的暴露的顶部表面积用于散热，而不管适用于紧密互连板的其它面积约束。 层叠的互连板可以被部分蚀刻或三维地形成以产生外围悬垂。

公开(公告)号：US20100044792A1

公开(公告)日：2010-02-25

申请号：US12321435

申请日：2009-01-21

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66734

Abstract: This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super-junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.

Abstract translation: 本发明公开了一种设置在半导体衬底上的半导体功率器件，包括具有填充所述深沟槽的外延层的多个深沟槽和覆盖半导体衬底上的所述深沟槽的顶表面之上的区域的同时生长的顶部外延层。 设置在所述顶部外延层中的多个沟槽MOSFET单元，顶部外延层用作体区，并且半导体衬底用作漏极区域，由此通过深沟槽中的外延层之间的电荷平衡实现超结效应 以及半导体衬底中与深沟槽横向相邻的区域。 每个沟槽MOSFET单元还包括沟槽栅极和栅极屏蔽掺杂剂区域，其设置在用于每个沟槽MOSFET单元的每个沟槽栅极的下方并基本对齐，用于在电压击穿期间屏蔽沟槽栅极。

公开(公告)号：US20100044791A1

公开(公告)日：2010-02-25

申请号：US12229250

申请日：2008-08-20

Applicant: Francois Hebert

Inventor： Francois Hebert

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66734

Abstract: This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of deep trenches. The deep trenches are filled with an epitaxial layer thus forming a top epitaxial layer covering areas above a top surface of the deep trenches covering over the semiconductor substrate. The semiconductor power device further includes a plurality of transistor cells disposed in the top epitaxial layer whereby a device performance of the semiconductor power device is dependent on a depth of the deep trenches and not dependent on a thickness of the top epitaxial layer. Each of the plurality of transistor cells includes a trench DMOS transistor cell having a trench gate opened through the top epitaxial layer and filled with a gate dielectric material.

公开(公告)号：US20100024213A1

公开(公告)日：2010-02-04

申请号：US12541881

申请日：2009-08-14

Applicant: Francois Hebert ,  Anup Bhalla

Inventor： Francois Hebert ,  Anup Bhalla

IPC: H01R43/02

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05017 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2224/48724 ,  H01L2224/48824 ,  H01L2224/85201 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.

Abstract translation: 公开了一种铜键合兼容的键合焊盘结构及其相关方法。 器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

公开(公告)号：US20090242973A1

公开(公告)日：2009-10-01

申请号：US12060096

申请日：2008-03-31

Applicant: Francois Hebert ,  Anup Bhalla

Inventor： Francois Hebert ,  Anup Bhalla

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734

Abstract: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed.

Abstract translation: 半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物 沿着源区域的侧壁和氧化物的侧壁设置。 还公开了制造这种装置的方法。

公开(公告)号：US20090134964A1

公开(公告)日：2009-05-28

申请号：US12011489

申请日：2008-01-25

Applicant: Francois Hebert ,  Tao Feng ,  Xiaotian Zhang ,  Jun Lu

Inventor： Francois Hebert ,  Tao Feng ,  Xiaotian Zhang ,  Jun Lu

IPC: H01F5/00

CPC classification number: H01F17/062

Abstract: A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.

Abstract translation: 公开了一种基于引线框架的分立功率电感器。 功率电感器包括顶部和底部引线框架，其引线围绕单个闭环磁芯形成线圈。 线圈包括顶部和底部引线框架的内部和外部接触部分之间的互连，磁芯夹在顶部和底部引线框架之间。 顶部引线框架和底部引线框架的引线的一部分具有大致非线性的阶梯状构造，使得顶部引线框架的引线将底部引线框架的相邻引线围绕磁芯耦合以形成线圈。