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172 条记录 (耗时 0.036 秒)

    Method for the manufacture of a MESFET comprising self aligned gate
    31.
    发明授权
    Method for the manufacture of a MESFET comprising self aligned gate 失效
    用于制造包括自对准栅极的MESFET的方法

    公开(公告)号：US4889827A

    公开(公告)日：1989-12-26

    申请号：US247662

    申请日：1988-09-22

    申请人： Josef Willer

    发明人： Josef Willer

    IPC分类号： H01L21/302 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/338 ,  H01L29/812

    CPC分类号： H01L29/66863 ,  H01L21/28587 ,  Y10S148/139 ,  Y10S148/14 ,  Y10S148/168

    摘要： A method for the manufacture of a MESFET comprising a gate that is self-aligned both with respect to the source and drain regions as well as with respect to the appertaining metallizations, whereby a first metal layer (21), a first dielectric layer (31), and a first lacquer mask layer are applied following doping of the carrier substrate. A trench producing an outer recess in the doping layer (11) is formed by anisotropic etching. A second dielectric layer is isotropically deposited and is anisotropically re-etched except for spacers (51/52) whereby an inner recess (double recess) is produced in the doping layer and, finally, the gate metal (22) is applied.

    摘要翻译： 一种用于制造MESFET的方法，包括相对于源极和漏极区域自对准的栅极以及相对于不同的金属化层的自对准栅极，由此第一金属层（21），第一介电层（31） ），并且在载体衬底的掺杂之后施加第一漆掩模层。 通过各向异性蚀刻形成在掺杂层（11）中产生外凹部的沟槽。 第二电介质层被各向同性地沉积，并且除了间隔物（51/52）之外是各向异性再蚀刻，由此在掺杂层中产生内部凹部（双凹槽），最后施加栅极金属（22）。

    Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module
    32.
    发明授权
    Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module 有权
    集成电路，对集成电路的存储单元阵列进行编程的方法以及存储器模块

    公开(公告)号：US07796449B2

    公开(公告)日：2010-09-14

    申请号：US12351023

    申请日：2009-01-09

    申请人： Josef Willer ,  Gert Koebernik

    发明人： Josef Willer ,  Gert Koebernik

    IPC分类号： G11C7/00

    CPC分类号： G11C16/22

    摘要： An integrated circuit having a memory cell arrangement with a plurality of memory cells and a memory cell arrangement controller is provided. The memory cell arrangement controller is configured such that during programming of at least one memory cell of the plurality of memory cells, at least one memory cell, which is arranged adjacent to the memory cell to be programmed, is driven to shield the memory cell to be programmed.

    摘要翻译： 提供具有多个存储单元的存储单元布置的集成电路和存储单元布置控制器。 存储单元布置控制器被配置为使得在对多个存储器单元中的至少一个存储单元进行编程期间，驱动与被编程的存储器单元相邻布置的至少一个存储单元，以将存储单元屏蔽到 被编程。

    Semiconductor memory having charge trapping memory cells and fabrication method thereof
    33.
    发明授权
    Semiconductor memory having charge trapping memory cells and fabrication method thereof 失效
    具有电荷捕获存储单元的半导体存储器及其制造方法

    公开(公告)号：US07662687B2

    公开(公告)日：2010-02-16

    申请号：US12110849

    申请日：2008-04-28

    申请人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl Heinz Kuesters

    发明人： Josef Willer ,  Thomas Mikolajick ,  Christoph Ludwig ,  Norbert Schulze ,  Karl Heinz Kuesters

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

    摘要： A semiconductor memory having charge trapping memory cells and fabrication method thereof. The direction of current flow of each channel region of the memory transistors runs transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive local interconnects of source-drain regions are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and connected to the bit lines, wherein gate electrodes are arranged in trenches at least partly formed in the memory substrate.

    摘要翻译： 一种具有电荷捕获存储单元的半导体存储器及其制造方法。 存储晶体管的每个通道区域的电流流动方向相对于相关字线横向延伸，位线布置在字线的顶侧，并以与之相隔离的方式布置，并且导电的局部 存在源极 - 漏极区域的互连，其在字线之间的间隔中以部分布置并且以与后者的电绝缘并且连接到位线的方式布置，其中栅极电极布置在至少部分地形成在存储器中的沟槽中 基质。

    Non-volatile memory cell and fabrication method
    37.
    再颁专利
    Non-volatile memory cell and fabrication method 有权
    非易失性存储单元及其制造方法

    公开(公告)号：USRE40532E1

    公开(公告)日：2008-10-07

    申请号：US11034444

    申请日：2005-01-11

    申请人： Josef Willer ,  Franz Hofmann ,  Armin Kohlhase ,  Christoph Ludwig

    发明人： Josef Willer ,  Franz Hofmann ,  Armin Kohlhase ,  Christoph Ludwig

    IPC分类号： H01L21/336 ,  H01L29/94

    CPC分类号： H01L27/11568 ,  H01L27/115

    摘要： Memory cell transistors with back-channel isolation are produced without using an SOI substrate. With the word line stack acting as a mask, the semiconductor material is etched on both sides of the world line, first anisotropically and then isotropically to widen the etch hole and form an undercut beneath the gate electrode and at a distance from the ONO storage layer forming the gate dielectric. The undercut is filled, whereby a buried oxide layer of at least 20 nm maximum thickness is formed underneath the channel region. The latter is p-doped at a density of at least 1017 cm−3.

    摘要翻译： 在不使用SOI衬底的情况下制造具有背沟道隔离的存储单元晶体管。 利用字线叠层作为掩模，半导体材料在世界线的两侧蚀刻，首先各向异性地，然后各向同性地加宽蚀刻孔，并在栅电极下方并在与ONO存储层一定距离处形成底切 形成栅极电介质。 填充底切，由此在通道区域的下方形成最大厚度为至少20nm的掩埋氧化物层。 后者以至少10 17 cm -3的密度进行p掺杂。

    Memory array having an interconnect and method of manufacture
    39.
    发明申请
    Memory array having an interconnect and method of manufacture 审中-公开
    具有互连和制造方法的存储器阵列

    公开(公告)号：US20080074927A1

    公开(公告)日：2008-03-27

    申请号：US11525547

    申请日：2006-09-22

    申请人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    发明人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A memory array includes first, second, third and forth memory cell strings. Each of the first, second, third, and fourth memory cell strings includes a number of serially-coupled memory cells, including a first memory cell and a last memory cell. A first interconnect is coupled to a first bit line and to each of the first, second, third and fourth memory cell strings. The first interconnect includes first, second, third and fourth string input select gates. Each input select gate has a first terminal coupled to the first bit line, and a second terminal coupled to one of the respective first, second, third or fourth memory cell strings.

    摘要翻译： 存储器阵列包括第一，第二，第三和第四存储器单元串。 第一，第二，第三和第四存储器单元串中的每一个包括多个串行耦合的存储器单元，包括第一存储单元和最后存储单元。 第一互连耦合到第一位线和第一，第二，第三和第四存储器单元串中的每一个。 第一互连包括第一，第二，第三和第四串输入选择门。 每个输入选择栅极具有耦合到第一位线的第一端子和耦合到相应的第一，第二，第三或第四存储器单元串之一的第二端子。

    Memory cell arrangements and methods of manufacturing memory cell arrangements
    40.
    发明申请
    Memory cell arrangements and methods of manufacturing memory cell arrangements 有权
    存储单元布置和制造存储单元布置的方法

    公开(公告)号：US20080073694A1

    公开(公告)日：2008-03-27

    申请号：US11526149

    申请日：2006-09-22

    申请人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    发明人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    IPC分类号： H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

    摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。