公开(公告)号：US20200381476A1

公开(公告)日：2020-12-03

申请号：US16425360

申请日：2019-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal

IPC: H01L27/22 ,  H01L27/24 ,  H01L23/528 ,  H01L45/00 ,  G11C11/16 ,  H01L43/10 ,  H01F41/32 ,  H01F10/32 ,  H01L43/02 ,  G11C13/00

Abstract: Structures for a bitcell of a non-volatile memory and methods of fabricating and using such structures. Non-volatile memory elements are arranged in a Wheatstone bridge arrangement having a first terminal and a second terminal. A first field-effect transistor is coupled with the first terminal of the Wheatstone bridge arrangement, and a second field-effect transistor is coupled with the second terminal of the Wheatstone bridge arrangement.

公开(公告)号：US10795082B1

公开(公告)日：2020-10-06

申请号：US16540452

申请日：2019-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Yusheng Bian ,  Theodore Letavic ,  Kenneth J. Giewont ,  Steven M. Shank

IPC: G02B6/124 ,  G02B6/12 ,  G02B6/13

Abstract: Structures that include a Bragg grating and methods of fabricating a structure that includes a Bragg grating. Bragg elements are positioned adjacent to a waveguide. The Bragg elements are separated by grooves that alternate with the Bragg elements. A dielectric layer includes portions positioned to close the grooves to define airgaps. The airgaps are respectively arranged between adjacent pairs of the Bragg elements. The Bragg elements may be used to form the Bragg grating.

公开(公告)号：US10746907B2

公开(公告)日：2020-08-18

申请号：US15945347

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Yusheng Bian

IPC: G02B5/18 ,  G02B6/30 ,  G02B6/34

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with structured cladding and methods of manufacture. A structure includes: a grating coupler in a dielectric material; a back end of line (BEOL) multilayer stack over the dielectric material; and a multi-layered cladding structure of alternating materials directly on the BEOL multilayer stack.

公开(公告)号：US10684530B1

公开(公告)日：2020-06-16

申请号：US16288634

申请日：2019-02-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Abu Thomas

IPC: G02F1/29

Abstract: Structures for an electro-optic modulator and methods of fabricating a structure for an electro-optic modulator. An electro-optic modulator is arranged over a portion of a waveguide core. The electro-optic modulator includes an electrode, an active layer arranged adjacent to the electrode, and a dielectric layer including a portion that has a lateral arrangement between the electrode and the active layer. The active layer is composed of a material having a refractive index that is a function of a bias voltage applied to the electrode and the active layer.

公开(公告)号：US20200012045A1

公开(公告)日：2020-01-09

申请号：US16026596

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/125 ,  G02B6/122 ,  G02B6/136

Abstract: Waveguide bends and methods of fabricating waveguide bends. A first waveguide bend is contiguous with a waveguide. A second waveguide bend is spaced from a surface at an inner radius of the first waveguide bend by a gap. The second waveguide bend may have a substantially concentric arrangement with the first waveguide bend.

公开(公告)号：US10411069B1

公开(公告)日：2019-09-10

申请号：US15898547

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.

公开(公告)号：US20190259808A1

公开(公告)日：2019-08-22

申请号：US15898547

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a first MTJ stack overlying a semiconductor substrate. The integrated circuit further includes a second lower MTJ stack spaced from the first lower MTJ stack and overlying the semiconductor substrate. The integrated circuit further includes a dielectric layer disposed between the first lower MTJ stack and the second lower MTJ stack. The dielectric layer is overlying the semiconductor substrate. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack, the dielectric layer, and the second lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack. The integrated circuit further includes a second upper MTJ stack overlying the spin orbit torque coupling layer and the second lower MTJ stack.

公开(公告)号：US10381406B1

公开(公告)日：2019-08-13

申请号：US15898555

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/04 ,  H01L43/14 ,  H01L43/06 ,  G11C11/18 ,  H01L43/10

CPC classification number: H01L27/228 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H01L43/04 ,  H01L43/065 ,  H01L43/10 ,  H01L43/14

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.

公开(公告)号：US10325812B2

公开(公告)日：2019-06-18

申请号：US15950291

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/45 ,  H01L21/02 ,  H01L21/283 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267 ,  H01L27/088 ,  H01L21/84 ,  H01L29/417 ,  H01L27/12

Abstract: A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.

公开(公告)号：US10056453B2

公开(公告)日：2018-08-21

申请号：US15217643

申请日：2016-07-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Srinivasa R. Banna ,  Deepak K. Nayak ,  Bartlomiej J. Pawlak

IPC: H01L29/06 ,  H01L23/00 ,  H01L29/20 ,  H01L29/16 ,  H01L29/267 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3065

CPC classification number: H01L29/0657 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/3083 ,  H01L23/562 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/267

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor wafers with reduced bowing and warping and methods of manufacture. The structure includes a substrate including plurality of trenches which have progressively different depths as they extend radially inwardly from an edge of the substrate towards a center of the substrate.