公开(公告)号：US09431300B1

公开(公告)日：2016-08-30

申请号：US14837222

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jia Zeng ,  Jongwook Kye ,  Harry J. Levinson

IPC: H01L21/82 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/522 ,  H01L29/66 ,  H01L27/088 ,  H01L29/45 ,  H01L21/00

CPC classification number: H01L21/823475 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L2027/11875

Abstract: A method of forming an ultra-regular layout with unidirectional M1 metal line and the resulting device are disclosed. Embodiments include forming first and second vertical gate lines, spaced from and parallel to each other; forming a M1 metal line parallel to and between the first and second gate lines; forming first, second, and third M0 metal segments perpendicular to the M1 metal line; connecting the first M0 metal segment to the M1 metal line and the second gate line; connecting the second M0 metal segment to the first gate line and the second gate line; connecting the third M0 metal segment to the first gate line and the M1 metal line; forming a first gate cut on the first gate line between the second and third M0 metal segments; and forming a second gate cut on the second gate line between the first and second M0 segments.

Abstract translation: 公开了一种用单向M1金属线形成超规则布局的方法及其结果。 实施例包括形成彼此间隔开并平行的第一和第二垂直栅极线; 形成平行于第一和第二栅极线之间的M1金属线; 形成垂直于M1金属线的第一，第二和第三M0金属段; 将第一M0金属段连接到M1金属线和第二栅极线; 将所述第二M0金属段连接到所述第一栅极线和所述第二栅极线; 将第三M0金属段连接到第一栅极线和M1金属线; 在所述第二和第三M0金属段之间的第一栅极线上形成第一栅极切割; 以及在第一和第二M0段之间的第二栅极线上形成第二栅极切割。

公开(公告)号：US09287131B2

公开(公告)日：2016-03-15

申请号：US14186396

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50 ,  H01L21/308 ,  H01L21/306 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  G03F1/70 ,  G03F7/00

CPC classification number: H01L21/3088 ,  G03F1/70 ,  G03F7/0002 ,  G06F17/5068 ,  H01L21/0274 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76877

Abstract: A method involving identifying a pattern for an overall target cut mask to be used in patterning line-type features that includes a target non-rectangular opening feature having an inner, concave corner, decomposing the overall target cut mask pattern into first and second sub-target patterns, wherein the first sub-target pattern comprises a first rectangular-shaped opening feature corresponding to a first portion, but not all, of the target non-rectangular opening feature and the second sub-target pattern comprises a second rectangular-shaped opening feature corresponding to a second portion, but not all, of the target non-rectangular opening feature, the first and second openings overlapping adjacent the inner, concave corner, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, wherein at least one of the first and second sets of mask data is generated based upon an identified contact-to-end-of-cut-line spacing rule.

Abstract translation: 一种涉及识别用于构图线型特征的整体目标切割掩模的图案的方法，所述线型特征包括具有内凹角的目标非矩形开口特征，将总体目标切割掩模图案分解为第一和第二子图， 目标图案，其中所述第一子目标图案包括与所述目标非矩形开口特征和所述第二子目标图案的第一部分但不是全部相对应的第一矩形开口特征，所述第一子目标图案包括第二矩形开口特征， 特征对应于目标非矩形开口特征的第二部分但不是全部，第一和第二开口与内凹角相邻重叠，并且生成对应于第一和第二子图的第一和第二组掩模数据， 目标图案，其中基于所识别的切割线间距规则，生成第一组和第二组掩模数据中的至少一个。

公开(公告)号：US09147653B2

公开(公告)日：2015-09-29

申请号：US14513834

申请日：2014-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry Levinson

IPC: H01L23/498 ,  H01L21/308 ,  H01L23/50 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/528

CPC classification number: H01L23/49838 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838 ,  H01L23/50 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for efficient off-track routing and the resulting device are disclosed. Embodiments include: providing a hardmask on a substrate; providing a plurality of first mandrels on the hardmask; providing a first spacer on each side of each of the first mandrels; providing a plurality of first non-mandrel regions of the substrate being separated from the first mandrels and between two of the first spacers, each of the first mandrels, first non-mandrel regions, and first spacers having a width equal to a distance; and providing a second mandrel having a width of at least twice the distance and being separated from one of the first non-mandrel regions by a second spacer.

Abstract translation: 公开了一种用于有效的非轨道路由的方法以及所得到的设备。 实施例包括：在基板上提供硬掩模; 在硬掩模上提供多个第一心轴; 在每个所述第一心轴的每一侧上提供第一间隔件; 提供所述基板的多个第一非心轴区域与所述第一心轴分开并且在所述第一间隔件中的两个之间，所述第一心轴，第一非心轴区域和第一间隔件中的每一个具有等于一定距离的宽度; 以及提供具有至少两倍距离的宽度的第二心轴，并且通过第二间隔件与第一非心轴区域之一分离。

公开(公告)号：US08954913B1

公开(公告)日：2015-02-10

申请号：US14043251

申请日：2013-10-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Soo Han Choi ,  Jongwook Kye ,  Harry J. Levinson

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G03F1/70 ,  G06F17/5068

Abstract: One method disclosed herein involves, among other things, generating a set of mandrel mask rules, block mask rules and a virtual, software-based non-mandrel-metal mask. The method also includes creating a set of virtual non-mandrel mask rules that is a replica of the mandrel mask rules, generating a set of metal routing design rules based upon the mandrel mask rules, the block mask rules and the virtual non-mandrel mask rules, generating the circuit routing layout based upon the metal routing design rules, decomposing the circuit routing layout into a mandrel mask pattern and a block mask pattern, generating a first set of mask data corresponding to the mandrel mask pattern, and generating a second set of mask data corresponding to the block mask pattern.

Abstract translation: 本文公开的一种方法尤其涉及生成一组心轴掩模规则，块掩模规则和基于软件的虚拟金属掩模。 该方法还包括创建一组虚拟非心轴掩模规则，该规则是心轴掩模规则的副本，基于心轴掩模规则，块掩模规则和虚拟非心轴掩模生成一组金属路由设计规则 规则，基于金属路由设计规则生成电路布线布局，将电路路由布局分解为心轴掩模图案和块掩模图案，产生对应于心​​轴掩模图案的第一组掩模数据，以及生成第二组 对应于块掩模图案的掩模数据。

公开(公告)号：US08637214B2

公开(公告)日：2014-01-28

申请号：US13725191

申请日：2012-12-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yunfei Deng ,  Jongwook Kye

IPC: G03F1/00 ,  G03F1/70

CPC classification number: G03F1/00 ,  G03B27/42 ,  G03F7/2024 ,  H01L21/0273

Abstract: Methods are provided for fabricating a semiconductor device. One method comprises providing a first pattern having a first polygon, the first polygon having a first tonality and having a first side and a second side, the first side adjacent to a second polygon having a second tonality, and the second side adjacent to a third polygon having the second tonality, and forming a second pattern by reversing the tonality of the first pattern. The method further comprises forming a third pattern from the second pattern by converting the second polygon from the first tonality to the second tonality forming a fourth pattern from the second pattern by converting the third polygon from the first tonality to the second tonality forming a fifth pattern by reversing the tonality of the third pattern, and forming a sixth pattern by reversing the tonality of the fourth pattern.

Abstract translation: 提供了制造半导体器件的方法。 一种方法包括提供具有第一多边形的第一图案，所述第一多边形具有第一音调并且具有第一侧和第二侧，所述第一侧邻近于具有第二音调的第二多边形，并且所述第二侧相邻于第三多边形 具有第二色调的多边形，并且通过反转第一图案的色调来形成第二图案。 该方法还包括通过从第二图案将第二多边形从第一图案转换成第二色调而将第二多边形从第一色调转换成第二色调以从第二图案转换成第二色调，从第二图案形成第三图案， 通过颠倒第三图案的音调，并通过反转第四图案的音调形成第六图案。

公开(公告)号：US10366917B2

公开(公告)日：2019-07-30

申请号：US15861799

申请日：2018-01-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xuelian Zhu ,  Jia Zeng ,  Chenchen Wang ,  Jongwook Kye

IPC: H01L21/48 ,  H01L21/768

Abstract: Methods of patterning metallization lines having variable widths in a metallization layer. A first mandrel layer is formed over a mask layer, with the mask layer overlying a second mandrel layer. The first mandrel layer is etched to form mandrel lines that have variable widths. The first non-mandrel trenches are etched in the mask layer, where the non-mandrel trenches have variable widths. The first mandrel lines are used to etch mandrel trenches in the mask layer, so that the mandrel lines and first non-mandrel lines define a mandrel pattern. The second mandrel layer is etched according to the mandrel pattern to form second mandrel lines, with the second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of non-mandrel trenches.

公开(公告)号：US10147714B2

公开(公告)日：2018-12-04

申请号：US15289401

申请日：2016-10-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yan Wang ,  Jia Zeng ,  Chenchen Wang ,  Wenhui Wang ,  Lei Yuan ,  Jongwook Kye

IPC: H01L27/02 ,  H01L21/768 ,  G06F17/50

Abstract: At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.

公开(公告)号：US09536778B2

公开(公告)日：2017-01-03

申请号：US14679060

申请日：2015-04-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Jongwook Kye ,  Harry J Levinson

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/532

CPC classification number: H01L21/76802 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257

Abstract: Self-aligned double patterning processes to produce metal route between and connecting conductive lines are disclosed. Embodiments include forming a hard mask over a dielectric layer; forming a patterning template including plural parallel linear elements on the hard mask, wherein said hard mask is exposed between adjacent parallel linear elements; forming a block mask covering a portion of said adjacent parallel linear elements and spaces therebetween; etching exposed portions of said hard mask through said block mask and said patterning template defining plural parallel lines; removing said block mask and said patterning template; forming a cut mask above said hard mask to define an opening perpendicular to and connecting two adjacent parallel lines; etching said hard mask through said cut mask and removing the cut mask; etching recesses in the dielectric layer through said hard mask; removing the hard mask; and filling said recesses with a conductive material.

Abstract translation: 公开了用于在导线之间产生金属路径的自对准双重图案化工艺。 实施例包括在电介质层上形成硬掩模; 在硬掩模上形成包括多个平行线形元件的图案化模板，其中所述硬掩模在相邻的平行线性元件之间露出; 形成覆盖所述相邻的平行线性元件的一部分和其间的空间的块掩模; 通过所述块掩模蚀刻所述硬掩模的暴露部分和限定多条平行线的所述图案化模板; 去除所述块掩模和所述图案化模板; 在所述硬掩模上形成切割掩模以限定垂直于并连接两个相邻平行线的开口; 通过所述切割掩模蚀刻所述硬掩模并除去切割的掩模; 通过所述硬掩模蚀刻介电层中的凹槽; 去除硬面膜; 并用导电材料填充所述凹部。

公开(公告)号：US20160336183A1

公开(公告)日：2016-11-17

申请号：US14712767

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Yuan ,  Jongwook Kye ,  Mahbub Rashed

IPC: H01L21/285 ,  H01L29/78 ,  H01L21/67 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L29/41791 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/11807 ,  H01L29/401 ,  H01L29/458 ,  H01L29/66795 ,  H01L29/785

Abstract: At least one method, apparatus and system disclosed herein for processing a semiconductor wafer using a continuous active area design for manufacturing a finFET device. A first gate structure of a continuous active area design is formed in a first layer of the wafer. A first hard mask layer is deposited. A portion of the first hard mask layer is removed based upon a first trench silicide (TS) pattern and a second TS pattern. A full stripe first trench silicide (TS) structure and a second TS structure are formed. A first TS capping layer is deposited above the first TS structure and a second TS capping. The first TS capping layer is removed and a source/drain contact structure (CA) is formed above the first TS structure in a second layer of the semiconductor wafer. A gate contact structure (CB) is formed above the gate structure in the second layer.

Abstract translation: 本文公开的至少一种方法，装置和系统，用于使用用于制造finFET器件的连续有源区域设计来处理半导体晶片。 连续有源区域设计的第一栅极结构形成在晶片的第一层中。 沉积第一个硬掩模层。 基于第一沟槽硅化物（TS）图案和第二TS图案去除第一硬掩模层的一部分。 形成全条纹第一沟槽硅化物（TS）结构和第二TS结构。 第一TS封装层沉积在第一TS结构上方，并且第二TS覆盖层。 去除第一TS封盖层，并且在半导体晶片的第二层中的第一TS结构之上形成源极/漏极接触结构（CA）。 栅极接触结构（CB）形成在第二层中的栅极结构的上方。

公开(公告)号：US20160335389A1

公开(公告)日：2016-11-17

申请号：US14712830

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Yuan ,  Yan Wang ,  Chenchen Wang ,  Jongwook Kye

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077

Abstract: At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received. The design comprises a functional cell. A first substitute functional cell for a first value of shift of a set of routing tracks respective to the boundary of the functional cell is provided. The first substitute functional cell comprises at least one pin moved by an amount of the first value. A determination is made as to whether an amount of shift of the set of routing tracks corresponds to the first value. The functional cell is replaced with the first substitute functional cell in response to a determination that the amount of shift of the set of routing tracks corresponds to the first value.

Abstract translation: 所公开的至少一种方法，装置和系统涉及用于集成电路装置的电路布局。 接收集成电路装置的设计。 该设计包括功能单元。 提供了与功能单元的边界相对应的一组路线轨迹的第一移位值的第一替代功能单元。 第一替代功能单元包括移动了第一值的量的至少一个销。 确定路由路径组的移位量是否对应于第一值。 响应于确定路由路径集合的偏移量对应于第一值，功能单元被第一替代功能单元替换。