公开(公告)号：US09436078B2

公开(公告)日：2016-09-06

申请号：US14609588

申请日：2015-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Obert Reeves Wood, II

IPC: G03F1/24 ,  G03F1/22

CPC classification number: G03F1/22 ,  G03F1/24 ,  G03F1/58

Abstract: Methods for creating a EUV photolithography mask with a thinner highly EUV absorbing absorber layer and the resulting device are disclosed. Embodiments include forming a multilayer reflector (MLR); forming first and second layers of a first EUV absorbing material over the MLR, the second layer being between the first layer and the MLR; and implanting the first layer with particles of a second EUV absorbing material, wherein the first EUV absorbing material is etchable and has a lower EUV absorption coefficient than the second EUV absorbing material, and wherein the implanted particles are substantially separated from each other.

Abstract translation: 公开了用于制造具有较薄的高度EUV吸收层的EUV光刻掩模和所得到的器件的方法。 实施例包括形成多层反射器（MLR）; 在所述MLR上形成第一EUV吸收材料的第一层和第二层，所述第二层位于所述第一层和所述MLR之间; 以及用第二EUV吸收材料的颗粒注入所述第一层，其中所述第一EUV吸收材料是可蚀刻的并且具有比所述第二EUV吸收材料更低的EUV吸收系数，并且其中所述注入的颗粒彼此基本上分离。

公开(公告)号：US20160162624A1

公开(公告)日：2016-06-09

申请号：US14685701

申请日：2015-04-14

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lei Sun ,  Wenhui Wang ,  Ryan Ryoung-Han Kim

IPC: G06F17/50 ,  G03F1/22 ,  G03F1/70 ,  H01L21/027

CPC classification number: G03F1/22 ,  G03F1/36 ,  G03F7/2045 ,  G06F17/5081 ,  H01L21/0274

Abstract: A method of optical proximity correction (OPC) in extreme ultraviolet lithography (EUV) lithography includes providing a patterned layout design including first and second design polygons that correspond with the pre-pattern opening, wherein the first and second design polygons are separated by a separation distance, and correcting the patterned layout design using OPC by generating (1) a third polygon that has dimensions corresponding to a combination of the first and second design polygons and the separation distance and (2) and filled polygon within the third polygon, thereby generating an OPC-corrected patterned layout design. EUV photomasks may be manufactured from the OPC-corrected patterned layout design, and integrated circuits may be fabricated using such EUV photomasks.

Abstract translation: 在极紫外光刻（EUV）光刻中的光学邻近校正（OPC）的方法包括提供图案化布局设计，其包括与预图案开口对应的第一和第二设计多边形，其中第一和第二设计多边形通过分离 距离，并且通过生成（1）具有对应于第一和第二设计多边形和分离距离的组合的尺寸的第三多边形以及（2）和第三多边形内的填充多边形来校正图案化布局设计，从而生成 OPC校正图案布局设计。 EUV光掩模可以由OPC校正的图案化布局设计制造，并且可以使用这种EUV光掩模来制造集成电路。

公开(公告)号：US09298081B2

公开(公告)日：2016-03-29

申请号：US13790727

申请日：2013-03-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Obert Reeves Wood, II

IPC: G03F1/24 ,  G02B5/20 ,  G02B5/22 ,  G02B5/02

CPC classification number: G03F1/24 ,  G02B5/0242 ,  G02B5/208 ,  G02B5/22

Abstract: A scattering enhanced thin absorber for a EUV reticle and a method of making thereof is disclosed. Embodiments include forming a multilayer on the upper surface of a substrate, forming a capping layer over the multilayer, forming one or more diffuse scattering layers over the capping layer, and etching the diffuse scattering layers to form a stack.

Abstract translation: 公开了一种用于EUV掩模版的散射增强型薄吸收体及其制造方法。 实施例包括在衬底的上表面上形成多层，在多层上形成覆盖层，在覆盖层上形成一个或多个漫散射层，并蚀刻扩散散射层以形成叠层。

公开(公告)号：US09140975B2

公开(公告)日：2015-09-22

申请号：US14106219

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Lei Sun ,  Chanro Park ,  Wenhui Wang ,  Hui Zang

IPC: G03F1/62 ,  G03F1/64 ,  G03F1/00 ,  G03F1/22

CPC classification number: G03F1/142 ,  G03F1/22 ,  G03F1/62 ,  G03F1/64

Abstract: A method of forming an improved EUV mask and pellicle with airflow between the area enclosed by the mask and pellicle and the area outside the mask and pellicle and the resulting device are disclosed. Embodiments include forming a frame around a patterned area on an EUV mask; forming a membrane over the frame; and forming holes in the frame.

Abstract translation: 公开了一种在由掩模和防护薄膜组成的区域与掩模和防护薄膜之间的区域以及所得到的装置之间形成改进的EUV掩模和防护薄膜组件的方法。 实施例包括在EUV掩模上的图案化区域周围形成框架; 在框架上形成膜; 并在框架中形成孔。

公开(公告)号：US10802393B2

公开(公告)日：2020-10-13

申请号：US15784408

申请日：2017-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Obert R. Wood, II ,  Genevieve Beique ,  Yulu Chen ,  Erik Verduijn ,  Francis Goodwin

IPC: G03F1/24 ,  G03F1/58 ,  G03F1/80

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an extreme ultraviolet (EUV) lithography mask and methods of manufacture. The EUV mask structure includes: a reflective layer; a capping material on the reflective layer; a buffer layer on the capping layer; alternating absorber layers on the buffer layer; and a capping layer on the top of the alternating absorber layers.

公开(公告)号：US20200312764A1

公开(公告)日：2020-10-01

申请号：US16363585

申请日：2019-03-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang Ning ,  Ruilong Xie ,  Lei Sun

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: Structures that include interconnects and methods of forming structures that include interconnects. A first interconnect is formed in a first trench in an interlayer dielectric layer, and a second interconnect in a second trench in the interlayer dielectric layer. The second interconnect is aligned along a longitudinal axis with the first interconnect. A dielectric region is arranged laterally arranged between the first interconnect and the second interconnect. The interlayer dielectric layer is composed of a first dielectric material, and the dielectric region is composed of a second dielectric material having a different composition than the first dielectric material.

公开(公告)号：US10782606B2

公开(公告)日：2020-09-22

申请号：US16022752

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yong Liang ,  Lei Sun ,  Yongan Xu ,  Craig D. Higgins

IPC: G03F1/22 ,  G03F7/20

Abstract: Disclosed are embodiments of a multi-layer stack and photolithography methods and systems that employ such a stack. The disclosed multi-layer stacks include a photoresist layer on an underlayer. The photoresist layer and underlayer are made of different materials, which are selected so that valence and conduction band offsets between the underlayer and photoresist layer create an effective electric field (i.e., so that the stack is “self-biased”). When areas of the photoresist layer are exposed to radiation during photolithography and the radiation passes through photoresist layer and excites electrons in the underlayer, this effective electric field facilitates movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer in a direction normal to the interface between the underlayer and the photoresist layer. Movement of the radiation-excited electrons from the underlayer into the radiation-exposed areas of the photoresist layer improves photoresist layer development and pattern resolution.

公开(公告)号：US20190318927A1

公开(公告)日：2019-10-17

申请号：US15954066

申请日：2018-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lei Sun ,  Xunyuan Zhang ,  Frank W. Mont ,  Shao Beng Law

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02

Abstract: The present disclosure relates to methods of protecting a structure of an integrated circuit (IC) from rework, and more particularly, to methods of protecting a structure of an IC without impacting the critical dimension or the profile of the structure. For example, a method of protecting a structure of an IC from rework may include forming a first layer on a second layer; forming one or more first openings in the first layer, the first openings exposing a top surface of the second layer; selectively growing a Group VIII metal within the one or more first openings, thereby forming one or more first plugs; forming one or more final openings in the first layer; and removing the one or more first plugs.

公开(公告)号：US10388652B2

公开(公告)日：2019-08-20

申请号：US15811961

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yongiun Shi ,  Lei Sun ,  Laertis Economikos ,  Ruilong Xie ,  Lars Liebmann ,  Chanro Park ,  Daniel Chanemougame ,  Min Gyu Sung ,  Hsien-Ching Lo ,  Haiting Wang

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06 ,  H01L27/02 ,  H01L21/762 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/027

Abstract: The disclosure provides integrated circuit (IC) structures with single diffusion break (SDB) abutting end isolation regions, and methods of forming the same. An IC structure may include: a plurality of fins positioned on a substrate; a plurality of gate structures each positioned on the plurality of fins and extending transversely across the plurality of fins; an insulator region positioned on the plurality of fins and laterally between the plurality of gate structures; at least one single diffusion break (SDB) positioned within the insulator region and one of the plurality of fins, the at least one SDB region extending from an upper surface of the substrate to an upper surface of the insulator region; and an end isolation region abutting a lateral end of the at least one SDB along a length of the plurality of gate structures, the end isolation region extending substantially in parallel with the plurality of fins.

公开(公告)号：US10153162B2

公开(公告)日：2018-12-11

申请号：US15284773

申请日：2016-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ryan Ryoung-Han Kim ,  Wenhui Wang ,  Azat Latypov ,  Tamer Coskun, Jr. ,  Lei Sun

IPC: H01L21/306 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/66

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method includes providing a circuit structure layer over a substrate and at least one etch layer over the circuit structure layer, in the at least one etch layer patterning at least one primary pattern feature having at least one primary pattern feature dimension and at least one assist pattern feature having at least one assist pattern feature dimension, where the primary pattern feature dimension is greater than the assist pattern feature dimension, reducing the at least one primary pattern feature dimension and closing the assist pattern feature to form an etch pattern, and etching a circuit structure feature using the etch pattern.