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    Integrated multiple gate length semiconductor device including self-aligned contacts
    32.
    发明授权
    Integrated multiple gate length semiconductor device including self-aligned contacts 有权
    集成多栅长半导体器件包括自对准触点

    公开(公告)号：US09466680B2

    公开(公告)日：2016-10-11

    申请号：US14825375

    申请日：2015-08-13

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Su Chen Fan ,  Balasubramanian Pranatharthiharan ,  Rajasekhar Venigalla

    IPC: H01L29/423 ,  H01L27/092 ,  H01L21/28 ,  H01L29/49 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/321 ,  H01L21/3213

    CPC classification number: H01L29/42372 ,  H01L21/28088 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/823807 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/1033 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/78

    Abstract: A multi-channel semiconductor device includes a first and second gate channels formed in a semiconductor substrate. The first gate channel has a first length and the second gate channel has a second length greater than the first length. A gate dielectric layer is formed in the first and second gate channels. A first plurality of work function metal layers is formed on the gate dielectric layer of the first gate channel. A second plurality of work function metal layers is formed on the gate dielectric layer of the second gate channel. A barrier layer is formed on each of the first and second plurality of work function metal layers, and the gate dielectric layer. The multi-channel semiconductor device further includes metal gate stacks formed on of the barrier layer such that the barrier layer is interposed between the metal gate stacks and the gate dielectric layer.

    Abstract translation: 多沟道半导体器件包括形成在半导体衬底中的第一和第二栅极沟道。 第一栅极沟道具有第一长度，并且第二栅极沟道具有大于第一长度的第二长度。 在第一和第二栅极通道中形成栅极电介质层。 在第一栅极沟道的栅介质层上形成第一多个功函数金属层。 在第二栅极沟道的栅极介电层上形成第二多个功函数金属层。 在第一和第二多个功函数金属层和栅介质层中的每一个上形成阻挡层。 多沟道半导体器件还包括形成在阻挡层上的金属栅极堆叠，使得阻挡层插入在金属栅极堆叠和栅极电介质层之间。

    SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER
    39.
    发明申请
    SELF-ALIGNED GATE TIE-DOWN CONTACTS WITH SELECTIVE ETCH STOP LINER 有权
    具有选择性止动衬片的自对准门盖降低接触

    公开(公告)号：US20170047418A1

    公开(公告)日：2017-02-16

    申请号：US14822490

    申请日：2015-08-10

    Applicant: GLOBALFOUNDRIES, INC.

    Inventor： Su Chen Fan ,  Lars W. Liebmann ,  Ruilong Xie

    IPC: H01L29/45 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/768

    CPC classification number: H01L23/535 ,  H01L21/31053 ,  H01L21/31058 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/7827 ,  H01L2221/1063

    Abstract: A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.

    Abstract translation: 形成栅极结合的方法包括暴露有源区以形成沟槽接触开口并在其中形成沟槽接触。 在沟槽触点和相邻栅极结构的间隔物上形成蚀刻停止层。 沉积层间电介质（ILD）以填满蚀刻停止层。 栅极结构的一侧上的ILD和蚀刻停止层被打开以提供暴露的蚀刻停止层部分。 栅极结构凹陷以露出栅极导体。 去除暴露的蚀刻停止层部分。 沉积导电材料以提供与栅极结构一侧上的沟槽接触的自对准接触，以形成到栅极导体下方的栅极接触，并且在ILD之间的有效区域之间形成水平连接 栅极导体和自对准触点。

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