公开(公告)号：US20150054078A1

公开(公告)日：2015-02-26

申请号：US13972348

申请日：2013-08-21

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/0649 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin.

Abstract translation: 本文公开的一种方法包括形成堆叠的材料层以形成栅极结构，执行第一蚀刻工艺以通过限定栅极结构的端面的材料层限定开口，在开口中形成栅极分离结构并执行 用于限定栅极结构的侧表面的第二蚀刻工艺。 本文公开的装置包括第一和第二有源区，其包括至少一个鳍状，第一和第二栅极结构，其中每个栅极结构具有端面，以及位于栅极结构之间的栅极分离结构，其中栅极的相对表面 分离结构邻接门结构的​​端面，并且其中门分离结构的上表面位于至少一个翅片的上表面上方。

公开(公告)号：US08883623B2

公开(公告)日：2014-11-11

申请号：US13654717

申请日：2012-10-18

Applicant: GLOBALFOUNDRIES, Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Pranatharthiharan Balasubramanian ,  Shom Ponoth

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L29/66545 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/6653

Abstract: Methods of facilitating replacement gate processing and semiconductor devices formed from the methods are provided. The methods include, for instance, providing a plurality of sacrificial gate electrodes with sidewall spacers, the sacrificial gate electrodes with sidewall spacers being separated by, at least in part, a first dielectric material, wherein the first dielectric material is recessed below upper surfaces of the sacrificial gate electrodes, and the upper surfaces of the sacrificial gate electrodes are exposed and coplanar; conformally depositing a protective film over the sacrificial gate electrodes, the sidewall spacers, and the first dielectric material; providing a second dielectric material over the protective film, and planarizing the second dielectric material, stopping on and exposing the protective film over the sacrificial gate electrodes; and opening the protective film over the sacrificial gate electrodes to facilitate performing a replacement gate process.

Abstract translation: 提供了便于更换栅极处理的方法和由该方法形成的半导体器件。 所述方法包括例如提供具有侧壁间隔物的多个牺牲栅电极，具有侧壁间隔物的牺牲栅电极至少部分地由第一介电材料隔开，其中第一介电材料凹入下 牺牲栅电极和牺牲栅电极的上表面暴露并共面; 在牺牲栅电极，侧壁间隔物和第一介电材料上保形地沉积保护膜; 在所述保护膜上提供第二电介质材料，并且平坦化所述第二电介质材料，停止所述保护膜并在所述牺牲栅电极上暴露所述保护膜; 并且在牺牲栅电极之上打开保护膜以便于执行替换浇口工艺。

公开(公告)号：US20140256106A1

公开(公告)日：2014-09-11

申请号：US14283409

申请日：2014-05-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Ali Khakifirooz ,  Thomas N. Adam ,  Kangguo Cheng ,  Shom Ponoth ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A dielectric metal compound liner can be deposited on a semiconductor fin prior to formation of a disposable gate structure. The dielectric metal compound liner protects the semiconductor fin during the pattering of the disposable gate structure and a gate spacer. The dielectric metal compound liner can be removed prior to formation of source and drain regions and a replacement gate structure. Alternately, a dielectric metal compound liner can be deposited on a semiconductor fin and a gate stack, and can be removed after formation of a gate spacer. Further, a dielectric metal compound liner can be deposited on a semiconductor fin and a disposable gate structure, and can be removed after formation of a gate spacer and removal of the disposable gate structure. The dielectric metal compound liner can protect the semiconductor fin during formation of the gate spacer in each embodiment.

公开(公告)号：US20140231885A1

公开(公告)日：2014-08-21

申请号：US13773397

申请日：2013-02-21

Applicant: GLOBALFOUNDRIES, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chanro Park ,  Shom Ponoth

IPC: H01L29/66 ,  H01L29/788

CPC classification number: H01L29/66477 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/788

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, a method for fabricating integrated circuits includes providing a sacrificial gate structure over a semiconductor substrate. The sacrificial gate structure includes two spacers and sacrificial gate material between the two spacers. The method recesses a portion of the sacrificial gate material between the two spacers. Upper regions of the two spacers are etched while using the sacrificial gate material as a mask. The method includes removing a remaining portion of the sacrificial gate material and exposing lower regions of the two spacers. A first metal is deposited between the lower regions of the two spacers. A second metal is deposited between the upper regions of the two spacers.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，用于制造集成电路的方法包括在半导体衬底上提供牺牲栅极结构。 牺牲栅极结构在两个间隔物之间​​包括两个间隔物和牺牲栅极材料。 该方法将牺牲栅极材料的一部分凹入两个间隔物之间​​。 在使用牺牲栅极材料作为掩模的同时蚀刻两个间隔物的上部区域。 该方法包括去除牺牲栅极材料的剩余部分并暴露两个间隔物的下部区域。 第一金属沉积在两个间隔物的下部区域之间。 第二金属沉积在两个间隔物的上部区域之间。

公开(公告)号：US09515163B2

公开(公告)日：2016-12-06

申请号：US14021594

申请日：2013-09-09

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66545 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed herein includes removing a sacrificial gate structure and forming a replacement gate structure in its place, after forming the replacement gate structure, forming a metal silicide layer on an entire upper surface area of each of a plurality of source/drain regions and, with the replacement gate structure in position, forming at least one source/drain contact structure for each of the plurality of source/drain regions, wherein the at least one source/drain contact structure is conductively coupled to a portion of the metal silicide layer and a dimension of the at least one source/drain contact structure in a gate width direction of the transistor is less than a dimension of the source/drain region in the gate width direction.

Abstract translation: 本文公开的一种方法包括在形成替代栅极结构之后，移除牺牲栅极结构并形成替代栅极结构，在多个源极/漏极区中的每一个的整个上表面区域上形成金属硅化物层， 其中所述替换栅极结构处于适当位置，为所述多个源极/漏极区域中的每一个形成至少一个源极/漏极接触结构，其中所述至少一个源极/漏极接触结构导电耦合到所述金属硅化物层的一部分，以及 晶体管的栅极宽度方向上的至少一个源极/漏极接触结构的尺寸小于栅极宽度方向上的源极/漏极区域的尺寸。

公开(公告)号：US09478549B2

公开(公告)日：2016-10-25

申请号：US14529332

申请日：2014-10-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC: H01L21/84 ,  H01L27/108 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L27/10826 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211

Abstract: An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

公开(公告)号：US09379198B2

公开(公告)日：2016-06-28

申请号：US14494699

申请日：2014-09-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chih-Chao Yang ,  David V. Horak ,  Charles W. Koburger ,  Shom Ponoth

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/768 ,  H01L29/78

CPC classification number: H01L29/42372 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76888 ,  H01L21/76897 ,  H01L29/495 ,  H01L29/517 ,  H01L29/78

Abstract: An integrated circuit structure with a selectively formed and at least partially oxidized metal cap over a gate. In one embodiment, an integrated circuit structure has: a substrate; a metal gate located over the substrate; at least one liner layer over the substrate and substantially surrounding the metal gate; and an at least partially oxidized etch stop layer located directly over the metal gate, the etch stop layer including at least one of cobalt (Co), manganese (Mn), tungsten (W), iridium (Ir), rhodium (Rh) or ruthenium (Ru).

Abstract translation: 一种在栅极上具有选择性地形成和至少部分氧化的金属盖的集成电路结构。 在一个实施例中，集成电路结构具有：基板; 位于衬底上方的金属栅极; 至少一个衬底层，并且基本上围绕着金属栅极; 以及位于金属栅极正上方的至少部分氧化的蚀刻停止层，所述蚀刻停止层包括钴（Co），锰（Mn），钨（W），铱（Ir），铑（Rh）或 钌（Ru）。

公开(公告)号：US20160126352A1

公开(公告)日：2016-05-05

申请号：US14994549

申请日：2016-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/84 ,  H01L29/08 ,  H01L27/12 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7848 ,  H01L21/76283 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847

Abstract: A substrate including a handle substrate, a lower insulator layer, a buried semiconductor layer, an upper insulator layer, and a top semiconductor layer is provided. Semiconductor fins can be formed by patterning a portion of the buried semiconductor layer after removal of the upper insulator layer and the top semiconductor layer in a fin region, while a planar device region is protected by an etch mask. A disposable fill material portion is formed in the fin region, and a shallow trench isolation structure can be formed in the planar device region. The disposable fill material portion is removed, and gate stacks for a planar field effect transistor and a fin field effect transistor can be simultaneously formed. Alternately, disposable gate structures and a planarization dielectric layer can be formed, and replacement gate stacks can be subsequently formed.

Abstract translation: 提供了包括手柄基板，下绝缘体层，埋入半导体层，上绝缘体层和顶部半导体层的基板。 半导体鳍片可以通过在去除鳍片区域中的上绝缘体层和顶部半导体层之后图案化掩埋半导体层的一部分而形成，而平面器件区域被蚀刻掩模保护。 在翅片区域形成一次性填充材料部分，并且可以在平面装置区域中形成浅沟槽隔离结构。 去除一次性填充材料部分，并且可以同时形成用于平面场效应晶体管和鳍式场效应晶体管的栅极叠层。 或者，可以形成一次性栅极结构和平坦化介电层，并且随后可以形成替换栅极堆叠。

公开(公告)号：US20160071928A1

公开(公告)日：2016-03-10

申请号：US14943522

申请日：2015-11-17

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/0649 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: A transistor device includes first and second spaced-apart active regions positioned in a semiconductor substrate, each of the respective first and second spaced-apart active regions having at least one fin. First and second spaced-apart gate structures are positioned above the respective first and second active regions, each of the first and second gate structures having end surfaces. A gate separation structure is positioned between the first and second spaced-apart gate structures, wherein first and second opposing surfaces of the gate separation structure abut an entirety of the respective end surfaces of the first and second spaced-apart gate structures, and wherein an upper surface of the gate separation structure is positioned at a greater height level above the semiconductor substrate than an upper surface of the at least one fin of each of the respective first and second spaced-apart active regions.

Abstract translation: 晶体管器件包括位于半导体衬底中的第一和第二间隔开的有源区，相应的第一和第二间隔开的有源区中的每一个具有至少一个鳍。 第一和第二间隔开的栅极结构位于相应的第一和第二有源区域的上方，第一和第二栅极结构中的每一个具有端面。 栅极分离结构位于第一和第二间隔开的栅极结构之间，其中栅极分离结构的第一和第二相对表面邻接第一和第二间隔开的栅极结构的相应端表面的整体，并且其中 栅极分离结构的上表面位于比半导体衬底的每个相应的第一和第二间隔开的有源区的至少一个鳍的上表面更高的高度上。

公开(公告)号：US09219153B2

公开(公告)日：2015-12-22

申请号：US13972348

申请日：2013-08-21

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Shom Ponoth ,  Juntao Li

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/0649 ,  H01L21/28008 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/785

Abstract: One method disclosed herein includes forming a stack of material layers to form gate structures, performing a first etching process to define an opening through the stack of materials that defines an end surface of the gate structures, forming a gate separation structure in the opening and performing a second etching process to define side surfaces of the gate structures. A device disclosed herein includes first and second active regions that include at least one fin, first and second gate structures, wherein each of the gate structures have end surfaces, and a gate separation structure positioned between the gate structures, wherein opposing surfaces of the gate separation structure abut the end surfaces of the gate structures, and wherein an upper surface of the gate separation structure is positioned above an upper surface of the at least one fin.

Abstract translation: 本文公开的一种方法包括形成堆叠的材料层以形成栅极结构，执行第一蚀刻工艺以通过限定栅极结构的端面的材料层限定开口，在开口中形成栅极分离结构并执行 用于限定栅极结构的侧表面的第二蚀刻工艺。 本文公开的装置包括第一和第二有源区，其包括至少一个鳍状，第一和第二栅极结构，其中每个栅极结构具有端面，以及位于栅极结构之间的栅极分离结构，其中栅极的相对表面 分离结构邻接门结构的​​端面，并且其中门分离结构的上表面位于至少一个翅片的上表面上方。