公开(公告)号：US20130277683A1

公开(公告)日：2013-10-24

申请号：US13976837

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

发明人： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC分类号： H01L29/778 ,  H01L29/66

CPC分类号： H01L29/7787 ,  G06F1/1633 ,  G06F1/189 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0254 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789 ,  H01L29/785 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451

摘要： Transistors for high voltage and high frequency operation. A non-planar, polar crystalline semiconductor body having a top surface disposed between first and second opposite sidewalls includes a channel region with a first crystalline semiconductor layer disposed over the first and second sidewalls. The first crystalline semiconductor layer is to provide a two dimensional electron gas (2DEG) within the channel region. A gate structure is disposed over the first crystalline semiconductor layer along at least the second sidewall to modulate the 2DEG. First and second sidewalls of the non-planar polar crystalline semiconductor body may have differing polarity, with the channel proximate to a first of the sidewalls. The gate structure may be along a second of the sidewalls to gate a back barrier. The polar crystalline semiconductor body may be a group III-nitride formed on a silicon substrate with the (10 10) plane on a (110) plane of the silicon.

摘要翻译： 用于高压和高频工作的晶体管。 具有设置在第一和第二相对侧壁之间的顶表面的非平面极性结晶半导体本体包括具有设置在第一和第二侧壁上的第一晶体半导体层的沟道区。 第一晶体半导体层是在沟道区内提供二维电子气（2DEG）。 栅极结构沿至少第二侧壁设置在第一晶体半导体层上方，以调制2DEG。 非平面极性结晶半导体主体的第一和第二侧壁可具有不同的极性，其中通道靠近第一侧壁。 栅极结构可以沿着侧壁中的第二侧面以栅极背栅。 极性结晶半导体体可以是在硅衬底上形成的III族氮化物，其中（10 10）面在硅的（110）平面上。

公开(公告)号：US09064709B2

公开(公告)日：2015-06-23

申请号：US13631569

申请日：2012-09-28

申请人： Han Wui Then ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

发明人： Han Wui Then ,  Sansaptak Dasgupta ,  Gerhard Schrom ,  Valluri R. Rao ,  Robert S. Chau

IPC分类号： H01L27/06 ,  H01L29/93 ,  H01L29/66 ,  H01L29/94 ,  H01L27/08 ,  H01L29/06 ,  H01L29/205 ,  H01L29/04 ,  H01L29/20

CPC分类号： H01L27/0605 ,  H01L27/0805 ,  H01L29/045 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66181 ,  H01L29/93 ,  H01L29/94

摘要： III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

摘要翻译： 集成了至少一个具有高击穿电压（BV）的III-N MOS电容器的III-N高压MOS电容器和片上系统（SoC）解决方案，以实现高压和/或高功率电路。 可以实现超过4V的击穿电压，避免了RFIC和/或PMIC中的串联耦合电容的任何需要。 在实施例中，包括其中在低于0V的阈值电压下形成二维电子气（2DEG）的GaN层的耗尽型III-N电容器与IV族晶体管架构单片集成，例如平面和非平面硅CMOS晶体管技术 。 在实施例中，蚀刻硅衬底以提供形成GaN层和III-N势垒层的（111）外延生长表面。 在实施例中，沉积高K电介质层，并且电容器端子触点被制成2DEG并且在电介质层上。

公开(公告)号：US08890264B2

公开(公告)日：2014-11-18

申请号：US13627971

申请日：2012-09-26

申请人： Gilbert Dewey ,  Robert S. Chau ,  Marko Radosavljevic ,  Han Wui Then ,  Scott B. Clendenning ,  Ravi Pillarisetty

发明人： Gilbert Dewey ,  Robert S. Chau ,  Marko Radosavljevic ,  Han Wui Then ,  Scott B. Clendenning ,  Ravi Pillarisetty

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L21/28

CPC分类号： H01L29/66803 ,  B82Y10/00 ,  H01L21/2233 ,  H01L21/228 ,  H01L21/28264 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/78681 ,  H01L29/78696

摘要： A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen. In nanowire embodiments, a non-directional nitrogen doping of a high-k gate dielectric interface is performed before or concurrently with a conformal gate electrode deposition through exposure of the gate dielectric to liquid, vapor, gaseous, plasma, or solid state sources of nitrogen. In embodiments, a gate electrode metal is conformally deposited over the gate dielectric and an anneal is performed to uniformly accumulate nitrogen within the gate dielectric along the non-planar III-V semiconductor interface.

摘要翻译： 具有非平面晶体管沟道区域的III-V族半导体表面的高k栅极电介质界面是非定向掺杂氮气的。 在纳米线实施例中，通过将栅极电介质暴露于液体，蒸气，气体，等离子体或固态氮源，在共形栅极电极沉积之前或同时进行高k栅介质界面的非定向氮掺杂 。 在实施例中，栅极电极金属被共形沉积在栅极电介质上，并且执行退火以沿着非平面III-V半导体界面均匀地在栅极电介质内积累氮。

公开(公告)号：US10290614B2

公开(公告)日：2019-05-14

申请号：US13977195

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L25/00 ,  H01L25/07 ,  H01L27/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L29/423 ,  H01L29/778 ,  H01L21/8252 ,  H01L21/8258

摘要： System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

公开(公告)号：US20130271208A1

公开(公告)日：2013-10-17

申请号：US13977195

申请日：2011-12-19

申请人： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Han Wui Then ,  Robert Chau ,  Valluri Rao ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L25/07 ,  H01L25/00

CPC分类号： H01L25/072 ,  H01L21/8252 ,  H01L21/8258 ,  H01L25/50 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

摘要： System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) that is capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits. In embodiments, the III-N transistor architecture is amenable to scaling to sustain a trajectory of performance improvements over many successive device generations. In embodiments, the III-N transistor architecture is amenable to monolithic integration with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. Planar and non-planar HEMT embodiments having one or more of recessed gates, symmetrical source and drain, regrown source/drains are formed with a replacement gate technique permitting enhancement mode operation and good gate passivation.

摘要翻译： 片上系统（SoC）解决方案使用基于能够实现高Ft和足够高击穿电压（BV）的III类氮化物（III-N）的晶体管技术将RFIC与PMIC集成，以实现高电压和/ 或高功率电路。 在实施例中，III-N晶体管架构适于缩放以维持许多连续器件世代的性能改进的轨迹。 在实施例中，III-N晶体管架构适于与IV类晶体管架构（诸如平面和非平面硅CMOS晶体管技术）的单片集成。 具有凹入栅极，对称源极和漏极，再生长源极/漏极中的一个或多个的平面和非平面HEMT实施例使用允许增强模式操作和良好栅极钝化的替代栅极技术形成。

公开(公告)号：US09236476B2

公开(公告)日：2016-01-12

申请号：US13997972

申请日：2011-12-28

申请人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L21/84 ,  H01L29/423 ,  H01L27/12 ,  G11C11/412 ,  H01L29/66 ,  H01L27/06

CPC分类号： H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

摘要： Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了用于堆叠存储器件的晶体管的技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的多个翅片结构，其中，多个翅片结构的单个翅片结构包括设置在半导体衬底上的第一隔离层， 第一隔离层，设置在第一沟道层上的第二隔离层和设置在第二隔离层上的第二沟道层，以及与第一沟道层电容耦合以控制通过第一沟道层的电流的栅极端子 用于第一晶体管，并与第二沟道层电容耦合，以控制通过第二沟道层的电流流向第二晶体管。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140035041A1

公开(公告)日：2014-02-06

申请号：US13997972

申请日：2011-12-28

申请人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

发明人： Ravi Pillarisetty ,  Charles C. Kuo ,  Han Wui Then ,  Gilbert Dewey ,  Willy Rachmady ,  Van H. Le ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Niloy Mukherjee

IPC分类号： H01L29/78 ,  H01L29/66 ,  G11C11/412

CPC分类号： H01L29/785 ,  G11C11/412 ,  H01L21/845 ,  H01L27/0688 ,  H01L27/1211 ,  H01L29/4232 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/78696

摘要： Embodiments of the present disclosure provide techniques and configurations for stacking transistors of a memory device. In one embodiment, an apparatus includes a semiconductor substrate, a plurality of fin structures formed on the semiconductor substrate, wherein an individual fin structure of the plurality of fin structures includes a first isolation layer disposed on the semiconductor substrate, a first channel layer disposed on the first isolation layer, a second isolation layer disposed on the first channel layer, and a second channel layer disposed on the second isolation layer, and a gate terminal capacitively coupled with the first channel layer to control flow of electrical current through the first channel layer for a first transistor and capacitively coupled with the second channel layer to control flow of electrical current through the second channel layer for a second transistor. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例提供了用于堆叠存储器件的晶体管的技术和配置。 在一个实施例中，一种装置包括半导体衬底，形成在半导体衬底上的多个翅片结构，其中，多个翅片结构的单个翅片结构包括设置在半导体衬底上的第一隔离层， 第一隔离层，设置在第一沟道层上的第二隔离层和设置在第二隔离层上的第二沟道层，以及与第一沟道层电容耦合以控制通过第一沟道层的电流的栅极端子 用于第一晶体管，并与第二沟道层电容耦合，以控制通过第二沟道层的电流流向第二晶体管。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20120249009A1

公开(公告)日：2012-10-04

申请号：US13506626

申请日：2012-05-03

申请人： Gabriel Walter ,  Milton Feng ,  Nick Holonyak, JR. ,  Han Wui Then ,  Chao-Hsin Wu

发明人： Gabriel Walter ,  Milton Feng ,  Nick Holonyak, JR. ,  Han Wui Then ,  Chao-Hsin Wu

IPC分类号： H05B37/00 ,  H01L33/62 ,  H01L33/60

CPC分类号： H01S5/06203 ,  B82Y20/00 ,  H01L33/0016 ,  H01L33/30 ,  H01L33/38 ,  H01S5/06213 ,  H01S5/183 ,  H01S5/1835 ,  H01S5/34313

摘要： A method including: providing a transistor structure that includes a base region of first semiconductor type between semiconductor emitter and collector regions of second semiconductor type; providing, in the base region, at least one region exhibiting quantum size effects; providing emitter, base, and collector electrodes respectively coupled with emitter, base, and collector regions; applying electrical signals, including a high frequency electrical signal component, with respect to the emitter, base, and collector electrodes to produce output spontaneous light emission from the base region, aided by the quantum size region, the output spontaneous light emission including a high frequency optical signal component representative of the high frequency electrical signal component; providing an optical cavity for the light emission in the region between the base and emitter electrodes; and scaling the lateral dimensions of the optical cavity to control the speed of light emission response to the high frequency electrical signal component.

摘要翻译： 一种方法，包括：提供晶体管结构，所述晶体管结构包括在半导体发射极和第二半导体类型的集电极区之间的第一半导体类型的基极区; 在碱性区域中提供至少一个呈现量子效应的区域; 提供分别与发射极，基极和集电极区耦合的发射极，基极和集电极电极; 对发射极，基极和集电极施加包括高频电信号分量的电信号，以在量子尺寸区域辅助下产生从基极区域输出的自发光发射，包括高频的输出自发光发射 光信号分量代表高频电信号分量; 在基极和发射极之间的区域中提供用于发光的光学腔; 以及缩放光腔的横向尺寸以控制对高频电信号分量的发光响应的速度。

公开(公告)号：US20100085995A1

公开(公告)日：2010-04-08

申请号：US12384772

申请日：2009-04-08

申请人： Milton Feng ,  Nick Holonyak,, JR. ,  Gabriel Walter ,  Han Wui Then

发明人： Milton Feng ,  Nick Holonyak,, JR. ,  Gabriel Walter ,  Han Wui Then

IPC分类号： H01S5/00 ,  H01L33/00

CPC分类号： H01S5/06203 ,  H01S5/3095

摘要： A method for producing light emission from a semiconductor device includes the following steps: providing a semiconductor base region disposed between a semiconductor emitter region and a semiconductor collector region that forms a tunnel junction adjacent the base region; providing, in the base region, a region exhibiting quantum size effects; providing an emitter terminal, a base terminal, and a collector terminal respectively coupled with the emitter region, the base region, and the collector region; and applying electrical signals with respect to the emitter terminal, the base terminal and the collector terminal to produce light emission from the base region.

摘要翻译： 一种用于从半导体器件产生发光的方法包括以下步骤：提供设置在半导体发射极区域和形成邻近基极区域的隧道结的半导体集电极区域之间的半导体基极区域; 在碱性区域中提供显示量子尺寸效应的区域; 提供分别与发射极区域，基极区域和集电极区域耦合的发射极端子，基极端子和集电极端子; 并且相对于发射极端子，基极端子和集电极端子施加电信号以产生从基极区域发出的光。

公开(公告)号：US08005124B2

公开(公告)日：2011-08-23

申请号：US12587895

申请日：2009-10-14

申请人： Han Wui Then ,  Gabriel Walter ,  Milton Feng ,  Nick Holonyak, Jr.

发明人： Han Wui Then ,  Gabriel Walter ,  Milton Feng ,  Nick Holonyak, Jr.

IPC分类号： H01S5/00

CPC分类号： H01S5/06203 ,  B82Y20/00 ,  H01S5/0427 ,  H01S5/10 ,  H01S5/14 ,  H01S5/34

摘要： A method for producing wide bandwidth laser emission responsive to high frequency electrical input signals, including the following steps: providing a heterojunction bipolar transistor device having collector, base, and emitter regions; providing at least one quantum size region in the base region, and enclosing at least a portion of the base region in an optical resonant cavity; coupling electrical signals, including the high frequency electrical input signals, with respect to the collector, base and emitter region, to cause laser emission from the transistor device; and reducing the operating beta of the transistor laser device to enhance the optical bandwidth of the laser emission in response to the high frequency electrical signals.

摘要翻译： 一种响应于高频电输入信号产生宽带宽激光发射的方法，包括以下步骤：提供具有集电极，基极和发射极区的异质结双极晶体管器件; 在所述基极区域中提供至少一个量子尺寸区域，并且在所述光学谐振腔中包围所述基极区域的至少一部分; 将包括高频电输入信号的电信号相对于集电极，基极和发射极区域耦合，以引起来自晶体管器件的激光发射; 并降低晶体管激光器件的运行β，以响应高频电信号增强激光发射的光学带宽。