公开(公告)号：US20140197516A1

公开(公告)日：2014-07-17

申请号：US13739914

申请日：2013-01-11

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC分类号： H01L21/66 ,  H01L29/06

CPC分类号： H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

摘要翻译： 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20140140131A1

公开(公告)日：2014-05-22

申请号：US13681133

申请日：2012-11-19

申请人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

发明人： Teng-Hao Yeh ,  Yen-Hao Shih ,  Yan-Ru Chen

IPC分类号： H01L29/788 ,  G11C5/06 ,  G11C16/04 ,  H01L21/28

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C16/0483 ,  G11C2213/71 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7926

摘要： A device on an integrated circuit includes a stack of alternating semiconductor lines and insulating lines, and a gate structure over the stack of semiconductor lines. The gate structure includes a vertical portion adjacent the stack on the at least one side, and horizontal extension portions between the semiconductor lines. Sides of the insulating lines can be recessed relative to sides of the semiconductor lines, so at least one side of the stack includes recesses between semiconductor lines. The horizontal extension portions can be in the recesses. The horizontal extension portions have inside surfaces adjacent the sides of the insulating lines, and outside surfaces that can be flush with the sides of the semiconductor lines. The device may include a second gate structure spaced away from the first mentioned gate structure, and an insulating element between horizontal extension portions of the second gate structure and the first mentioned gate structure.

摘要翻译： 集成电路中的器件包括交替的半导体线路和绝缘线路的堆叠以及在半导体线路堆叠上的栅极结构。 栅极结构包括在至少一个侧面上与堆叠相邻的垂直部分和半导体线之间的水平延伸部分。 绝缘线的边可以相对于半导体线的侧面凹陷，因此堆叠的至少一侧包括半导体线之间的凹槽。 水平延伸部分可以在凹槽中。 水平延伸部具有与绝缘线的侧面相邻的内表面以及可与半导体线的侧面齐平的外表面。 器件可以包括与第一提到的栅极结构间隔开的第二栅极结构，以及在第二栅极结构的水平延伸部分和第一个提到的栅极结构之间的绝缘元件。

公开(公告)号：US20130119455A1

公开(公告)日：2013-05-16

申请号：US13294852

申请日：2011-11-11

申请人： SHIH-HUNG CHEN ,  Hang-Ting Lue ,  Yen-Hao Shih

发明人： SHIH-HUNG CHEN ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/1157 ,  H01L27/11578

摘要： A manufacturing method for a memory array includes first forming a multilayer stack of dielectric material on a plurality of semiconductor strips, and then exposing the multilayer stack in switch transistor regions. The multilayer stacks exposed in the switch transistor regions are processed to form gate dielectric structures that are different than the dielectric charge trapping structures. Word lines and select lines are then formed. A 3D array of dielectric charge trapping memory cells includes stacks of NAND strings of memory cells. A plurality of switch transistors are coupled to the NAND strings, the switch transistors including gate dielectric structures wherein the gate dielectric structures are different than the dielectric charge trapping structures.

摘要翻译： 一种用于存储器阵列的制造方法包括首先在多个半导体条上形成多层电介质材料，然后在开关晶体管区域中暴露多层叠层。 在开关晶体管区域中暴露的多层堆叠被处理以形成不同于介电电荷俘获结构的栅介质结构。 然后形成字线和选择线。 介质电荷俘获存储器单元的3D阵列包括存储器单元的NAND串的堆叠。 多个开关晶体管耦合到NAND串，开关晶体管包括栅极电介质结构，其中栅极电介质结构不同于介电电荷俘获结构。

公开(公告)号：US08374019B2

公开(公告)日：2013-02-12

申请号：US12985253

申请日：2011-01-05

申请人： Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

发明人： Chao-I Wu ,  Yen-Hao Shih ,  Ming-Hsiu Lee

IPC分类号： G11C11/00

CPC分类号： H01L45/06 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C14/00 ,  G11C2013/0083 ,  G11C2013/0092 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.

摘要翻译： 一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。 预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。 设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

公开(公告)号：US08026136B2

公开(公告)日：2011-09-27

申请号：US11964322

申请日：2007-12-26

申请人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Min-Ta Wu ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/8238 ,  H01L21/311

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518

摘要： Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×1011/cm−2, and methods for forming such memory cells.

摘要翻译： 存储单元包括：半导体衬底，具有由沟道区分开的至少两个源极/漏极区域; 设置在通道区域上方的电荷捕获结构; 以及设置在电荷捕获结构上方的栅极; 其中所述电荷捕获结构包括底部绝缘层，第一电荷俘获层和第二电荷俘获层，其中所述底部绝缘层和所述基底之间的界面的氢浓度小于约3×1011 / cm -2，以及形成这种记忆单元的方法。

公开(公告)号：US07911856B2

公开(公告)日：2011-03-22

申请号：US12471411

申请日：2009-05-25

申请人： Ming-Hsiu Lee ,  Yen-Hao Shih

发明人： Ming-Hsiu Lee ,  Yen-Hao Shih

IPC分类号： G11C7/00

CPC分类号： G11C13/0023 ,  G11C13/00 ,  G11C13/0004 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/792

摘要： A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.

摘要翻译： 公开了访问存储器单元的方法。 第一信号被发送到至少一个层选择晶体管。 基于第一信号激活至少一个层选择晶体管。 基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

公开(公告)号：US07824991B2

公开(公告)日：2010-11-02

申请号：US11334249

申请日：2006-01-18

申请人： Yen-Hao Shih ,  Shih-Chin Lee

发明人： Yen-Hao Shih ,  Shih-Chin Lee

IPC分类号： H01L21/336 ,  H01L21/31

CPC分类号： H01L21/28282 ,  H01L29/517 ,  H01L29/518 ,  Y10S438/954

摘要： A MOSFET fabrication process comprises nitridation of the dielectric silicon interface so that silicon-dangling bonds are connected with nitrogen atoms creating silicon—nitrogen bonds, which are stronger than silicon-hydrogen bonds. A tunnel dielectric is formed on the substrate. A nitride layer is then formed over the tunnel dielectric layer. The top of the nitride layer is then converted to an oxide and the interface between the substrate and the tunnel dielectric is nitrided simultaneously with conversion of the nitride layer to oxide.

摘要翻译： MOSFET制造工艺包括电介质硅界面的氮化，使得硅 - 悬挂键与氮原子连接，产生比硅 - 氢键更强的硅 - 氮键。 在基板上形成隧道电介质。 然后在隧道介电层上形成氮化物层。 然后将氮化物层的顶部转化为氧化物，并且衬底和隧道电介质之间的界面同时氮化氮化物层与氧化物的氮化。

公开(公告)号：US07763935B2

公开(公告)日：2010-07-27

申请号：US11159269

申请日：2005-06-23

申请人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

发明人： Yen-Hao Shih ,  Shih-Chin Lee ,  Jung-Yu Hsieh ,  Erh-Kun Lai ,  Kuang-Yeu Hsieh

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

摘要： A method of fabricating a non-volatile memory device at least comprises steps as follows. First, a substrate on which a bottom dielectric layer is formed is provided. Then, impurities are introduced through the bottom dielectric layer to the substrate, so as to form a plurality of spaced doped regions on the substrate. The structure is thermally annealed for pushing the spaced doped regions to diffuse outwardly. After annealing, a charge trapping layer is formed on the bottom dielectric layer, and a top dielectric layer is formed on the charge trapping layer. Finally, a gate structure (such as a polysilicon layer and a silicide) is formed on the top dielectric layer.

摘要翻译： 一种制造非易失性存储器件的方法至少包括以下步骤。 首先，提供形成有底部电介质层的基板。 然后，通过底部电介质层将杂质引入衬底，以在衬底上形成多个间隔开的掺杂区域。 该结构被热退火以推动间隔开的掺杂区域向外扩散。 退火后，在底部电介质层上形成电荷捕捉层，在电荷捕获层上形成顶部电介质层。 最后，在顶部电介质层上形成栅极结构（如多晶硅层和硅化物）。

公开(公告)号：US07560762B2

公开(公告)日：2009-07-14

申请号：US11209437

申请日：2005-08-23

申请人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Chia-Hua Ho ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L29/80

CPC分类号： H01L27/115 ,  G11C16/0483 ,  H01L27/11521

摘要： A NAND-type flash memory device includes asymmetric floating gates overlying respective wordlines. A given floating gate is sufficiently coupled to its respective wordline such that a large gate (i.e., wordline) bias voltage will couple the floating gate with a voltage which can invert the channel under the floating gate. The inversion channel under the floating gate can thus serve as the source/drain. As a result, the memory device does not need a shallow junction, or an assist-gate. In addition, the memory device exhibits relatively low floating gate-to-floating gate (FG-FG) interference.

摘要翻译： NAND型闪存器件包括覆盖相应字线的非对称浮动栅极。 给定的浮动栅极被充分地耦合到其相应的字线，使得大的栅极（即，字线）偏置电压将使浮动栅极与可以反转浮动栅极下方的沟道的电压耦合。 因此，浮置栅极下的反相通道可以作为源极/漏极。 结果，存储器件不需要浅结或辅助栅。 此外，存储器件具有相对较低的浮置栅极至浮置栅极（FG-FG）干扰。

公开(公告)号：US20080290397A1

公开(公告)日：2008-11-27

申请号：US11753850

申请日：2007-05-25

申请人： Tzu-Hsuan Hsu ,  Ming-Hsiang Hsueh ,  Yen-Hao Shih ,  Chia-Wei Wu

发明人： Tzu-Hsuan Hsu ,  Ming-Hsiang Hsueh ,  Yen-Hao Shih ,  Chia-Wei Wu

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L21/28282 ,  H01L29/42352 ,  H01L29/66833 ,  H01L29/792

摘要： A memory cell is disposed on a substrate having plurality of isolation structures that define at least a fin structure in the substrate, wherein the surface of the fin structure is higher than that of the isolation structures. The memory cell includes a gate, a charge trapping structure, a protection layer and two source/drain regions. The gate is disposed on the substrate,and straddled the fin structure. The charge trapping structure is disposed between the gate and the fin structure. The protection layer is disposed between the upper portion of the fin structure and the gate separating the charge trapping structure. The source/drain regions are disposed in the fin structure at both sides of the gate.

摘要翻译： 存储单元设置在具有多个隔离结构的衬底上，所述隔离结构在衬底中至少限定翅片结构，其中鳍结构的表面高于隔离结构的表面。 存储单元包括栅极，电荷俘获结构，保护层和两个源极/漏极区域。 栅极设置在基板上，并跨接在翅片结构上。 电荷捕获结构设置在栅极和鳍结构之间。 保护层设置在翅片结构的上部和分离电荷捕获结构的栅极之间。 源极/漏极区域设置在栅极两侧的鳍结构中。