公开(公告)号：US11195787B2

公开(公告)日：2021-12-07

申请号：US15045687

申请日：2016-02-17

Applicant: Infineon Technologies AG

Inventor： Ngoc-Hoa Huynh ,  Franz-Xaver Muehlbauer ,  Claus Waechter ,  Veronika Huber ,  Dominic Maier ,  Thomas Kilger ,  Saverio Trotta ,  Ashutosh Baheti ,  Georg Meyer-Berg ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/367 ,  H01L23/538 ,  H01Q9/28 ,  H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01L21/56 ,  H01Q9/26

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

公开(公告)号：US11145563B2

公开(公告)日：2021-10-12

申请号：US16447610

申请日：2019-06-20

Applicant: Infineon Technologies AG

Inventor： Christian Geissler ,  Walter Hartner ,  Claus Waechter ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00

Abstract: A method comprises providing a least one semiconductor component, wherein each of the at least one semiconductor component comprises: a semiconductor chip, wherein the semiconductor chip comprises a first main surface and a second main surface opposite the first main surface, and a sacrificial layer arranged above the opposite second main surface of the semiconductor chip. The method further comprises encapsulating the at least one semiconductor component with an encapsulation material. The method further comprises removing the sacrificial material, wherein above each of the at least one semiconductor chip a cutout is formed in the encapsulation material. The method further comprises arranging at least one lid above the at least one cutout, wherein a closed cavity is formed by the at least one cutout and the at least one lid above each of the at least one semiconductor chip.

公开(公告)号：US10916484B2

公开(公告)日：2021-02-09

申请号：US16014745

申请日：2018-06-21

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Francesca Arcioni ,  Christian Geissler ,  Walter Hartner ,  Gerhard Haubner ,  Thorsten Meyer ,  Martin Richard Niessner ,  Maciej Wojnowski

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L23/538 ,  H01L21/56

Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

公开(公告)号：US10692824B2

公开(公告)日：2020-06-23

申请号：US16173702

申请日：2018-10-29

Applicant: Infineon Technologies AG

Inventor： Rudolf Lachner ,  Linus Maurer ,  Maciej Wojnowski

IPC: H01L23/66 ,  H01Q9/04 ,  H01L23/31 ,  H01L23/00 ,  H01Q1/22

Abstract: A semiconductor radar module includes an integrated circuit (IC) radar device embedded within a wafer level package compound layer, the wafer level package compound layer extending at least partially lateral to the IC radar device. An interface layer abutting the wafer level package compound layer comprises a redistribution layer coupled to the IC radar device for connecting the IC radar device externally. An underfill material extends between the interface layer and an external substrate and abuts the interface layer and the external substrate. The interface layer is disposed between the wafer level package compound layer and the underfill material.

公开(公告)号：US20180374769A1

公开(公告)日：2018-12-27

申请号：US16014745

申请日：2018-06-21

Applicant: Infineon Technologies AG

Inventor： Robert Fehler ,  Francesca Arcioni ,  Christian Geissler ,  Walter Hartner ,  Gerhard Haubner ,  Thorsten Meyer ,  Martin Richard Niessner ,  Maciej Wojnowski

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: An electronic device is disclosed. In one example, the electronic device includes a solder ball, a dielectric layer comprising an opening, and a redistribution layer (RDL) comprising an RDL pad connected with the solder ball. The RDL pad including at least one void, the void being disposed at least in partial in an area of the RDL pad laterally outside of the opening of the dielectric layer.

公开(公告)号：US09922946B2

公开(公告)日：2018-03-20

申请号：US15480751

申请日：2017-04-06

Applicant: Infineon Technologies AG

Inventor： Ernst Seler ,  Maciej Wojnowski ,  Walter Hartner ,  Josef Boeck

IPC: H01L23/66 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01Q13/08

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01Q13/08 ,  H01L2924/00

Abstract: A method of manufacturing a semiconductor device package includes placing a semiconductor chip on a carrier, covering the semiconductor chip with an encapsulation material to form an encapsulation body, providing a microwave component having at least one electrically conducting wall structure integrated in the encapsulation body, and forming an electrical interconnect configured to electrically couple the semiconductor chip and the microwave component.

公开(公告)号：US20170236776A1

公开(公告)日：2017-08-17

申请号：US15045687

申请日：2016-02-17

Applicant: Infineon Technologies AG

Inventor： Ngoc-Hoa Huynh ,  Franz-Xaver Muehlbauer ,  Claus Waechter ,  Veronika Huber ,  Dominic Maier ,  Thomas Kilger ,  Saverio Trotta ,  Ashutosh Baheti ,  Georg Meyer-Berg ,  Maciej Wojnowski

IPC: H01L23/498 ,  H01L23/367 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49822 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3672 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/18162 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/265 ,  H01Q9/285 ,  H01Q21/061 ,  H01Q21/065

Abstract: A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

公开(公告)号：US20170162476A1

公开(公告)日：2017-06-08

申请号：US15367920

申请日：2016-12-02

Applicant: Infineon Technologies AG

Inventor： Thorsten MEYER ,  Klaus Pressel ,  Maciej Wojnowski

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/31 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/561 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49541 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/18162

Abstract: An electronic device comprising a semiconductor package having a first main surface region and a second main surface region and comprising a semiconductor chip comprising at least one chip pad in the second main surface region and a connector block comprising at least one first electrically conductive through connection and at least one second electrically conductive through connection extending with different cross-sectional areas between the first main surface region and the second main surface region and being arranged side-by-side with the semiconductor chip.

公开(公告)号：US09653426B2

公开(公告)日：2017-05-16

申请号：US15146090

申请日：2016-05-04

Applicant: Infineon Technologies AG

Inventor： Ernst Seler ,  Maciej Wojnowski ,  Walter Hartner ,  Josef Boeck

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/96 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01Q13/08 ,  H01L2924/00

Abstract: A method of manufacturing an array of semiconductor device packages includes placing a plurality of semiconductor chips on a temporary carrier, covering the plurality of semiconductor chips with an encapsulation material to form an encapsulation body, providing a plurality of microwave components each including at least one electrically conducting wall structure integrated in the encapsulation body, forming a plurality of electrical interconnects each configured to electrically couple a semiconductor chip and a microwave component, and separating the encapsulation body into single semiconductor device packages each including a semiconductor chip, a microwave component and an electrical interconnect.

公开(公告)号：US20160240495A1

公开(公告)日：2016-08-18

申请号：US15137594

申请日：2016-04-25

Applicant: Infineon Technologies AG

Inventor： Rudolf Lachner ,  Linus Maurer ,  Maciej Wojnowski

IPC: H01L23/66

CPC classification number: H01L23/66 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/12 ,  H01L24/19 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6677 ,  H01L2223/6683 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/351 ,  H01Q1/2283 ,  H01Q9/0407 ,  H01Q9/045 ,  H01Q9/0457 ,  H01L2924/00

Abstract: A semiconductor module comprises an integrated circuit device, the IC device embedded in a compound material, wherein the compound material at least partially extends lateral to the IC device. The semiconductor module further comprises interconnect structures arranged lateral to the IC device to provide at least one external electrical contact; a patch antenna structure integrated in the semiconductor module and electrically connected to the IC device and a layer interfacing the IC device and the compound, wherein the layer comprises first and second planar metal structures coupled to the IC device, wherein the first planar metal structure is electrically connected to the IC device and the interconnect structures and wherein the second planar metal structure is electrically connected to the IC device and the patch antenna structure.

Abstract translation: 半导体模块包括集成电路器件，嵌入复合材料中的IC器件，其中复合材料至少部分地延伸到IC器件的侧面。 半导体模块还包括布置在IC器件侧面的互连结构以提供至少一个外部电触点; 集成在半导体模块中并且电连接到IC器件的贴片天线结构和与IC器件和化合物接口的层，其中该层包括耦合到IC器件的第一和第二平面金属结构，其中第一平面金属结构是 电连接到IC器件和互连结构，并且其中第二平面金属结构电连接到IC器件和贴片天线结构。