公开(公告)号：US20150081984A1

公开(公告)日：2015-03-19

申请号：US14554532

申请日：2014-11-26

Applicant: Intel Corporation

Inventor： Robert G. Blankenship ,  Bahaa Fahim ,  Robert Beers ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Herbert H. Hum ,  Jeff Willey

IPC: G06F12/08

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

Abstract translation: 接收到要引用第一代理并请求特定的内存行以独占状态被缓存的请求。 发送窥探请求用于一个或多个其他代理。 接收到一个窥探响应，该响应是引用第二个代理，窥探响应包括对与特定的存储器行相对应的修改的高速缓存行的存储器的回写。 一个完整的发送被发送到第一个代理，其中完整的是基于回写来包括特定的存储器行的数据。

公开(公告)号：US12197357B2

公开(公告)日：2025-01-14

申请号：US17556853

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20240012772A1

公开(公告)日：2024-01-11

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  G06F9/46 ,  G06F13/40 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808

CPC classification number: G06F13/22 ,  H04L49/15 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/4286 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30145 ,  G06F13/4221 ,  G06F12/0806 ,  G06F12/0833 ,  G06F9/466 ,  G06F13/4022 ,  G06F9/44505 ,  G06F13/4282 ,  G06F1/3287 ,  G06F13/4068 ,  G06F11/1004 ,  G06F13/4291 ,  H04L9/0662 ,  G06F12/0808 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US11604730B2

公开(公告)日：2023-03-14

申请号：US16939197

申请日：2020-07-27

Applicant: Intel Corporation

Inventor： Rahul Pal ,  Philip Abraham ,  Ajaya Durg ,  Bahaa Fahim ,  Yen-Cheng Liu ,  Sanilkumar Mm

IPC: G06F12/08 ,  G06F12/0815 ,  G06F11/10 ,  G06F12/0893

Abstract: A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

公开(公告)号：US20200210315A1

公开(公告)日：2020-07-02

申请号：US16721868

申请日：2019-12-19

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Swadesh Choudhary

IPC: G06F11/34 ,  G06F11/14 ,  G06F11/36

Abstract: In one embodiment, a processor comprises a fabric interconnect to couple a first cache agent to at least one of a memory controller or an input/output (I/O) controller; and a first cache agent comprising a cache controller coupled to a cache; and a trace and capture engine to periodically capture a snapshot of state information associated with the first cache agent; trace events to occur at the first cache agent in between captured snapshots; and send the captured snapshots and traced events via the fabric interconnect to the memory controller or I/O controller for storage at a system memory or storage device.

公开(公告)号：US10474526B2

公开(公告)日：2019-11-12

申请号：US15282711

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Min Huang ,  Zhiguo Wang

IPC: G06F11/10 ,  G06F12/0811 ,  G11C29/44 ,  G11C29/00 ,  G06F12/0868 ,  G06F12/0875 ,  G11C29/52 ,  G11C29/04

Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

公开(公告)号：US20190047579A1

公开(公告)日：2019-02-14

申请号：US15942466

申请日：2018-03-31

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Riccardo Mariani ,  Dean Mulla ,  Robert Gottlieb

IPC: B60W50/023 ,  B60R16/023 ,  B60W50/02

Abstract: Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180095823A1

公开(公告)日：2018-04-05

申请号：US15282711

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Min Huang ,  Zhiguo Wang

IPC: G06F11/10 ,  G06F3/06 ,  G06F12/0811 ,  G11C29/52

Abstract: A cache controller id disclosed, The cache controller includes circuitry to receive a request to access data in a target location of a last level cache of a processor on a processor package, identify an in-field failure in the target location of the last level cache, perform, in response to the identification of the in-field failure, an in-field repair, including circuitry to write in-field repair information to a non-volatile memory on the processor package and external to the processor, the non-volatile memory including circuitry to store in-field repair information. Systems and methods are also disclosed.

公开(公告)号：US09921989B2

公开(公告)日：2018-03-20

申请号：US14707656

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： Krishnakumar Ganapathy ,  Yen-Cheng Liu ,  Antonio Juan ,  Steven R. Page ,  Jeffrey D. Chamberlain ,  Pau Cabre ,  Bahaa Fahim ,  Gunnar Gaubatz

IPC: G06F13/00 ,  G06F13/40 ,  G06F15/78 ,  G06F13/42 ,  G06F9/44

CPC classification number: G06F13/4022 ,  G06F9/4411 ,  G06F13/4036 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/7825

Abstract: In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.

公开(公告)号：US09910807B2

公开(公告)日：2018-03-06

申请号：US15583563

申请日：2017-05-01

Applicant: Intel Corporation

Inventor： Robert G. Blankenship ,  Geeyarpuram N. Santhanakrishnan ,  Yen-Cheng Liu ,  Bahaa Fahim ,  Ganapati N. Srinivasa

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/161 ,  G06F13/4282

Abstract: Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed on a main board including multiple CPU sockets linked in communication via CPU socket-to-socket interconnect links forming a CPU socket-to-socket ring interconnect. The CPU's are also configured to transfer data between one another by sending data via the CPU socket-to-socket interconnects. Data may be transferred using a packetized protocol, such as QPI, and the CPU's may also be configured to support coherent memory transactions across CPU's.