公开(公告)号：US09658963B2

公开(公告)日：2017-05-23

申请号：US14582121

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Yen-Cheng Liu

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/0831

CPC classification number: G06F12/0862 ,  G06F12/0835 ,  G06F12/0884 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/6026

Abstract: A speculative read request is received from a host device over a buffered memory access link for data associated with a particular address. A read request is sent for the data to a memory device. The data is received from the memory device in response to the read request and the received data is sent to the host device as a response to a demand read request received subsequent to the speculative read request.

公开(公告)号：US20170004098A1

公开(公告)日：2017-01-05

申请号：US15039468

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/42 ,  G06F12/14

CPC classification number: G06F13/1663 ,  G06F12/1475 ,  G06F13/385 ,  G06F13/4282 ,  G06F2212/1052 ,  G06F2213/0026 ,  Y02D10/14 ,  Y02D10/151

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

Abstract translation: 共享存储器控制器用于通过数据链路从多个独立节点服务加载和存储从数据链路接收的操作，以提供对共享存储器资源的访问。 要允许多个独立节点中的每一个访问共享存储器资源的相应部分。 在数据链路上发送互连协议数据和存储器访问协议数据，可以定义和识别互连协议数据和存储器访问协议数据之间的转换。

公开(公告)号：US20160283375A1

公开(公告)日：2016-09-29

申请号：US14670578

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/08 ,  G06F13/16 ,  G06F13/42 ,  G06F3/06

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

Abstract translation: 共享存储器控制器通过共享存储器链路从另一个第一共享存储器控制器接收飞行，其中，飞行包括节点标识符（ID）字段和共享存储器的特定行的地址。 节点ID字段标识第一个共享存储器控制器对应于一个源的源。 此外，从至少第二共享存储器控制器的地址字段确定第二共享存储器控制器，其中第二共享存储器控制器连接到对应于特定行的存储器元件。 根据路由路径，使用共享存储器链路将闪存转发到第二共享存储器控制器

公开(公告)号：US20210303482A1

公开(公告)日：2021-09-30

申请号：US17170619

申请日：2021-02-08

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US11113196B2

公开(公告)日：2021-09-07

申请号：US16140482

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/08 ,  G06F3/06 ,  G06F12/084 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

公开(公告)号：US10915468B2

公开(公告)日：2021-02-09

申请号：US15039468

申请日：2013-12-26

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US20190108124A1

公开(公告)日：2019-04-11

申请号：US16140482

申请日：2018-09-24

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/084 ,  G06F3/06 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/42 ,  G06F13/16

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US10163508B2

公开(公告)日：2018-12-25

申请号：US15055153

申请日：2016-02-26

Applicant: Intel Corporation

Inventor： Woojong Han ,  Mohamed Arafa ,  Brian S. Morris ,  Mani Prakash ,  James K. Pickett ,  John K. Grooms ,  Bruce Querbach ,  Edward L Payton ,  Dong Wang

IPC: G11C5/06 ,  G11C14/00 ,  G11C5/02 ,  G11C5/14

Abstract: Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.

公开(公告)号：US20180365438A1

公开(公告)日：2018-12-20

申请号：US15946401

申请日：2018-04-05

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

IPC: G06F21/62 ,  G06F21/60 ,  G06F21/64 ,  G06F21/78

CPC classification number: G06F21/62 ,  G06F12/1441 ,  G06F21/602 ,  G06F21/64 ,  G06F21/74 ,  G06F21/78 ,  G06F2221/2113

Abstract: A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

公开(公告)号：US10102886B2

公开(公告)日：2018-10-16

申请号：US15269657

申请日：2016-09-19

Applicant: Intel Corporation

Inventor： John H. Crawford ,  Brian S. Morris ,  Sreenivas Mandava ,  Raj K. Ramanujan

IPC: G11C7/02 ,  G06F13/16 ,  G11C11/406

Abstract: Examples are disclosed for probabilistic dynamic random access memory (DRAM) row repair. In some examples, using a row hammer limit for DRAM and a maximum activation rate for the DRAM a probabilistic row hammer detection value may be determined. The probabilistic row hammer detection value may then be used such that a probability is acceptably low that a given activation to an aggressor row of the DRAM causes the row hammer limit to be exceeded before a scheduled row refresh is performed on one or more victim rows associated with the aggressor row. Other examples are described and claimed.