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    A SCALABLE POLYLITHIC ON-PACKAGE INTEGRATABLE APPARATUS AND METHOD
    32.
    发明申请
    A SCALABLE POLYLITHIC ON-PACKAGE INTEGRATABLE APPARATUS AND METHOD 有权

    公开(公告)号：US20230110247A1

    公开(公告)日：2023-04-13

    申请号：US17977236

    申请日：2022-10-31

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Dinesh Somasekhar ,  Shekhar Y. Borkar

    IPC: H01L23/532 ,  H01L21/78

    Abstract: Described is an apparatus which comprises: a first die including: a processing core; a crossbar switch coupled to the processing core; and a first edge interface coupled to the crossbar switch; and a second die including: a first edge interface positioned at a periphery of the second die and coupled to the first edge interface of the first die, wherein the first edge interface of the first die and the first edge interface of the second die are positioned across each other; a clock synchronization circuit coupled to the second edge interface; and a memory interface coupled to the clock synchronization circuit.

    Low latency statistical data bus inversion for energy reduction
    33.
    发明授权
    Low latency statistical data bus inversion for energy reduction 有权

    公开(公告)号：US10853300B2

    公开(公告)日：2020-12-01

    申请号：US15475571

    申请日：2017-03-31

    Applicant: Intel Corporation

    Inventor： Vivek Kozhikkottu ,  Shankar Ganesh Ramasubramanian ,  Kon-Woo Kwon ,  Dinesh Somasekhar

    IPC: G06F13/42 ,  G06F13/36 ,  G06F13/40

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.

    Architecture For On-Die Interconnect
    36.
    发明申请
    Architecture For On-Die Interconnect 审中-公开
    架构互连

    公开(公告)号：US20160173413A1

    公开(公告)日：2016-06-16

    申请号：US15042402

    申请日：2016-02-12

    Applicant: Intel Corporation

    Inventor： Surhud Khare ,  Ankit More ,  Dinesh Somasekhar ,  David S. Dunning

    IPC: H04L12/933 ,  H01L23/528 ,  H01L23/522

    CPC classification number: H04L49/109 ,  H01L23/5221 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In an embodiment, an apparatus includes: a plurality of islands configured on a semiconductor die, each of the plurality of islands having a plurality of cores; and a plurality of network switches configured on the semiconductor die and each associated with one of the plurality of islands, where each network switch includes a plurality of output ports, a first set of the output ports are each to couple to the associated network switch of an island via a point-to-point interconnect and a second set of the output ports are each to couple to the associated network switches of a plurality of islands via a point-to-multipoint interconnect. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，一种装置包括：配置在半导体管芯上的多个岛，多个岛中的每一个具有多个核; 以及多个网络交换机，其配置在所述半导体管芯上并且各自与所述多个岛中的一个岛相关联，其中每个网络交换机包括多个输出端口，所述输出端口的第一组各自耦合到相关联的网络交换机 经由点对点互连的岛屿和第二组输出端口各自经由点对多点互连耦合到多个岛的相关网络交换机。 描述和要求保护其他实施例。

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