公开(公告)号：US12100662B2

公开(公告)日：2024-09-24

申请号：US17127304

申请日：2020-12-18

Applicant: Intel Corporation

Inventor： Zhiguo Qian ,  Gerald Pasdast ,  Peipei Wang ,  Daniel Krueger ,  Edward Burton

IPC: H01L23/538 ,  H01L21/50 ,  H01L23/50 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/50 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: An integrated circuit (IC) package, comprising a substrate that comprises a bridge die embedded within a dielectric. A first die comprising a first input/output (I/O) transmitter and a second die comprising a second I/O receiver and electrically coupled to the bridge die. A first signal trace and a first power conductor are within the bridge die. The first signal trace and the first power conductor are electrically coupled to the first I/O transmitter and the second I/O receiver. The first signal trace is to carry a digital signal and the first power conductor to provide a voltage for the second I/O receiver to read the digital signal.

公开(公告)号：US20240274542A1

公开(公告)日：2024-08-15

申请号：US18628525

申请日：2024-04-05

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US12014990B2

公开(公告)日：2024-06-18

申请号：US18132865

申请日：2023-04-10

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US20240183884A1

公开(公告)日：2024-06-06

申请号：US18076352

申请日：2022-12-06

Applicant: Intel Corporation

Inventor： Vikrant Thigle ,  Vijay Anand Mathiyalagan ,  Anand Haridass ,  Arun Chandrasekhar ,  Gerald Pasdast

IPC: G01R19/00 ,  G01R19/25 ,  G05F1/46

CPC classification number: G01R19/0038 ,  G01R19/25 ,  G05F1/46

Abstract: Embodiments herein relate to a chiplet or other die which includes multiple sense points within the die and components for digitizing and outputting sensed voltages of the sense points. In one approach, an analog-to-digital converter (ADC) is coupled to each sense point, and a multiplexer is coupled to the outputs of the ADCs. A select signal for the multiplexer can be received from an external control unit which selects one of the sense points based on information such as a current workflow of the die. The selected sense point can change as the workflow changes. The optimal sense point can be determined by comparing the voltage of each sense point and selecting the sense point with the lowest voltage. The sensed voltage is provided to a voltage regulator as a feedback signal to optimize control of the power supply of the die.

公开(公告)号：US11899615B2

公开(公告)日：2024-02-13

申请号：US18102568

申请日：2023-01-27

Applicant: Intel Corporation

Inventor： Nevine Nassif ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Gerald Pasdast ,  Siva Soumya Eachempati ,  Tejpal Singh ,  Ankush Varma ,  Mahesh K. Kumashikar ,  Srikanth Nimmagadda ,  Carleton L. Molnar ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  William R. Halleck ,  George Z Chrysos ,  John R. Ayers ,  Dheeraj R. Subbareddy

IPC: G06F1/00 ,  G06F15/78 ,  G06F1/10 ,  G06F15/167 ,  G06F1/04 ,  G06F1/12 ,  G06F9/38 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F15/7889 ,  G06F1/04 ,  G06F1/10 ,  G06F1/12 ,  G06F9/3869 ,  G06F9/5038 ,  G06F15/167 ,  G06F15/17312

Abstract: Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

公开(公告)号：US20230245972A1

公开(公告)日：2023-08-03

申请号：US18132865

申请日：2023-04-10

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US20220327084A1

公开(公告)日：2022-10-13

申请号：US17853502

申请日：2022-06-29

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Swadesh Choudhary ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

IPC: G06F13/42 ,  G06F13/40 ,  G06F11/10

Abstract: Protocol layer logic in a protocol stack receives an indication that a particular mode is to be utilized on a die-to-die (D2D) link connecting a first device to a second device. The protocol layer logic generates data to be sent on the D2D link to adapt the particular data format to a flit format defined for use on the D2D link in the particular mode, the flit format comprises providing a set of reserved fields to be completed by an adapter block positioned between the protocol circuitry and a physical layer block. The data in the flit format is sent to the data to the adapter block to prepare the data for transmission over the D2D link.

公开(公告)号：US20220084949A1

公开(公告)日：2022-03-17

申请号：US17536804

申请日：2021-11-29

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US11205630B2

公开(公告)日：2021-12-21

申请号：US16586158

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Patrick Morrow ,  Johanna Swan ,  Shawna Liff ,  Mauro Kobrinksy ,  Van Le ,  Gerald Pasdast

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L25/18 ,  H01L25/00 ,  H01L21/768 ,  H01L21/82 ,  H01L23/48

Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.

公开(公告)号：US11094672B2

公开(公告)日：2021-08-17

申请号：US16586145

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Johanna Swan ,  Shawna Liff ,  Patrick Morrow ,  Gerald Pasdast ,  Van Le

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/522 ,  H01L23/00 ,  H01L25/00

Abstract: Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.