公开(公告)号：US20230178513A1

公开(公告)日：2023-06-08

申请号：US17543419

申请日：2021-12-06

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel A. Elsherbini ,  Christopher M. Pelto ,  Georgios Dogiamis ,  Bradley A. Jackson ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/50 ,  H01L24/80 ,  H01L24/96 ,  H01L24/16 ,  H01L2225/06572 ,  H01L2224/80896 ,  H01L2224/80895 ,  H01L2224/16145 ,  H01L2224/16227

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third layer between the first layer and the second layer, the third layer comprising conductive routing traces in a dielectric. A first interface is between the first layer and the third layer and includes first interconnects having a first pitch of less than 10 micrometers between adjacent ones of the first interconnects, a second interface is between the second layer and the third layer and includes second interconnects having a second pitch of less than 10 micrometers between adjacent ones of the second interconnects, and the routing traces in the third layer are to provide lateral electrical coupling between the first interconnects and the second interconnects.

公开(公告)号：US20230073026A1

公开(公告)日：2023-03-09

申请号：US17470189

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Kimin Jun ,  Shawna M. Liff ,  Johanna M. Swan ,  Han Wui Then

IPC: H01L23/528 ,  H01L23/522

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.

公开(公告)号：US20220415904A1

公开(公告)日：2022-12-29

申请号：US17355449

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Wilfred Gomes ,  Van H. Le ,  Kimin Jun ,  Hui Jae Yoo

IPC: H01L27/108 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Embodiments of the present disclosure provide power to backend memory of an IC device from the back side of the device. An example IC device with back-side power delivery for backend memory includes a frontend layer with a plurality of frontend components such as frontend transistors, a backend layer (that may include a plurality of layers) with backend memory (e.g., with one or more eDRAM arrays), and a back-side power delivery structure with a plurality of back-side interconnects electrically coupled to the backend memory, where the frontend layer is between the back-side power delivery structure and the backend layer.

公开(公告)号：US11251156B2

公开(公告)日：2022-02-15

申请号：US15773514

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Brennen K. Mueller ,  Patrick Morrow ,  Kimin Jun ,  Paul B. Fischer ,  Daniel Pantuso

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L21/762 ,  H01L21/84 ,  H01L23/485 ,  H01L21/48 ,  H01L23/48 ,  H01L23/498 ,  H01L27/12

Abstract: An apparatus including a circuit structure including a device stratum; one or more electrically conductive interconnect levels on a first side of the device stratum and coupled to ones of the transistor devices; and a substrate including an electrically conductive through silicon via coupled to the one or more electrically conductive interconnect levels so that the one or more inter connect levels are between the through silicon via and the device stratum. A method including forming a plurality of transistor devices on a substrate, the plurality of transistor devices defining a device stratum; forming one or more interconnect levels on a first side of the device stratum; removing a portion of the substrate; and coupling a through silicon via to the one or more interconnect levels such that the one or more interconnect levels is disposed between the device stratum and the through silicon via.

公开(公告)号：US11201221B2

公开(公告)日：2021-12-14

申请号：US16999508

申请日：2020-08-21

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Rishabh Mehandru ,  Aaron D. Lilak ,  Kimin Jun

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/40 ,  H01L21/225 ,  H01L21/265

Abstract: An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.

公开(公告)号：US20200235061A1

公开(公告)日：2020-07-23

申请号：US16651888

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Patrick Morrow ,  Henning Braunisch ,  Kimin Jun ,  Brennen Mueller ,  Shawna M. Liff ,  Johanna M. Swan ,  Paul B. Fischer

IPC: H01L23/64 ,  H01L23/34 ,  H01L23/66 ,  H01L49/02

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may a die having a front side and a back side, the die comprising a first material and conductive contacts at the front side; and a thermal layer attached to the back side of the die, the thermal layer comprising a second material and a conductive pathway, wherein the conductive pathway extends from a front side of the thermal layer to a back side of the thermal layer.

公开(公告)号：US10361090B2

公开(公告)日：2019-07-23

申请号：US15120720

申请日：2014-09-24

Applicant: INTEL CORPORATION

Inventor： Kimin Jun ,  Patrick Morrow ,  Donald Nelson

IPC: H01L21/308 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/06

Abstract: A grid comprising a first set of grid lines and a second set of grid lines is formed on a substrate using a first lithography process. At least one of the first set of grid lines and the second set of grid lines are selectively patterned to define a vertical device feature using a second lithography process.

公开(公告)号：US10297592B2

公开(公告)日：2019-05-21

申请号：US15625714

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L23/538 ,  H01L21/768 ,  H01L27/06 ,  H01L27/11 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L21/822 ,  H01L29/78

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.

公开(公告)号：US20190006171A1

公开(公告)日：2019-01-03

申请号：US15748619

申请日：2015-08-28

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Ravi Pillarisetty ,  Kimin Jun ,  Patrick Morrow ,  Valluri R. Rao ,  Paul B. Fischer ,  Robert S. Chau

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8258 ,  H01L27/085 ,  H01L23/48 ,  H01L27/06 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L21/0254 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/187 ,  H01L21/76251 ,  H01L21/8258 ,  H01L23/481 ,  H01L27/0605 ,  H01L27/085 ,  H01L29/2003 ,  H01L29/7786

Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

公开(公告)号：US20170287905A1

公开(公告)日：2017-10-05

申请号：US15625714

申请日：2017-06-16

Applicant: INTEL CORPORATION

Inventor： Patrick Morrow ,  Kimin Jun ,  M. Clair Webb ,  Donald W. Nelson

IPC: H01L27/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L29/78 ,  H01L23/538 ,  H01L27/088 ,  H01L27/11 ,  H01L27/12 ,  H01L21/768 ,  H01L21/84

CPC classification number: H01L27/0688 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/845 ,  H01L23/5386 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1116 ,  H01L27/1211 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least one transistor level within the 3D IC. In certain embodiments the local inter-level interconnect intersects a gate electrode or a source/drain region of at least one transistor and extends through at least one inter-level dielectric layer disposed between a first and second transistor level in the 3D IC. Local inter-level interconnects may advantageously make a direct vertical connection between transistors in different levels of the 3D IC without being routed laterally around the footprint (i.e., lateral, or planar, area) of either the overlying or underlying transistor level that is interconnected.