公开(公告)号：US20190189182A1

公开(公告)日：2019-06-20

申请号：US15843480

申请日：2017-12-15

Applicant: International Business Machines Corporation

Inventor： Brian J. Connolly ,  Kyu-Hyoun Kim ,  Warren E. Maule

IPC: G11C11/4074

CPC classification number: G11C11/4074 ,  G11C5/04 ,  G11C5/14 ,  G11C5/141 ,  G11C5/147 ,  G11C29/702

Abstract: A memory subsystem is disclosed comprising at least one memory module, the memory module having a substrate to which a plurality of memory chips is mounted and a voltage regulator, the voltage regulator receiving a power supply signal from a system power supply and outputting two or more power signals, each power signal providing a different, regulated voltage, which regulated voltages are each routed to each of the memory chips; and a redundant voltage regulator external to and not mounted on the memory module and configured to output two or more power signals, providing external different, regulated voltages which are the same voltages as the voltages output by the voltage regulator on the memory module, and supplying the two or more signals to the memory module.

公开(公告)号：US10168923B2

公开(公告)日：2019-01-01

申请号：US15138629

申请日：2016-04-26

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Adam J. McPadden ,  Anuwat Saetow

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/406 ,  G06F11/20 ,  G11C14/00 ,  G11C5/04

Abstract: An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.

公开(公告)号：US09899067B2

公开(公告)日：2018-02-20

申请号：US15406655

申请日：2017-01-13

Applicant: International Business Machines Corporation

Inventor： John S. Bialas, Jr. ,  David D. Cadigan ,  Stephen P. Glancy ,  Warren E. Maule ,  Gary A. Van Huben

IPC: G11C7/22 ,  G11C7/10 ,  G11C29/50

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/1066 ,  G11C7/1093 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093 ,  G11C29/50012 ,  G11C2029/5004 ,  G11C2207/2254

Abstract: A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A temporal calibration mechanism reduces the time and resources for calibration by reducing the number tests needed to sufficiently determine the boundaries of the data eye of the memory device. For one or more values of the voltage reference, the temporal calibration mechanism performs a minimal number of tests to find the edges of the data eye for the hold and setup times.

公开(公告)号：US20180018217A1

公开(公告)日：2018-01-18

申请号：US15207679

申请日：2016-07-12

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Marc A. Gollub ,  Warren E. Maule ,  Lucas W. Mulkey ,  Anuwat Saetow

IPC: G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F11/10

Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects and error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.

公开(公告)号：US20170308309A1

公开(公告)日：2017-10-26

申请号：US15138629

申请日：2016-04-26

Applicant: International Business Machines Corporation

Inventor： Edgar R. Cordero ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Adam J. McPadden ,  Anuwat Saetow

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/406 ,  G06F11/20 ,  G11C14/00

CPC classification number: G06F3/0619 ,  G06F3/0608 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0685 ,  G06F11/2015 ,  G06F2201/805 ,  G06F2201/86 ,  G11C5/04 ,  G11C14/0018

Abstract: An aspect includes coherency management between volatile memory and non-volatile memory in a through-silicon via (TSV) module of a computer system. A plurality of TSV write signals is simultaneously provided to the volatile memory and the non-volatile memory. A plurality of values of the TSV write signals is captured within a buffer of the non-volatile memory corresponding to a data set written to the volatile memory. Storage space is freed within the buffer as the data set corresponding to the values of the TSV write signals stored within the buffer is written to a non-volatile memory array within the non-volatile memory.

公开(公告)号：US20170235632A1

公开(公告)日：2017-08-17

申请号：US15583019

申请日：2017-05-01

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/10 ,  H03M13/19 ,  H03M13/15

CPC classification number: G06F11/1044 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0673 ,  G06F11/0727 ,  G06F11/076 ,  G06F11/0766 ,  G06F11/0772 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1024 ,  G06F11/1048 ,  H03M13/1515 ,  H03M13/19

Abstract: Embodiments of the present disclosure provide an approach for monitoring the health and predicting the failure of dynamic random-access memory (DRAM) devices with embedded error-correcting code (ECC). Additional registers are embedded on the DRAM device to store information about the DRAM, such as the number and location of soft errors detected by the device. When the DRAM device detects a soft error, it will update the information stored in the additional registers. A controller compares the information stored in the additional registers to associated thresholds. In some embodiments, after comparing the information to the associated thresholds, the controller may determine whether to schedule a repair action. In other embodiments, the controller may determine whether to alert the memory controller that the DRAM may be failing.

公开(公告)号：US09626242B2

公开(公告)日：2017-04-18

申请号：US14751382

申请日：2015-06-26

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/00 ,  G08C25/00 ,  H03M13/00 ,  H04L1/00 ,  G06F11/10 ,  G06F3/06

CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/00 ,  G06F11/1048 ,  G06F11/1076 ,  G06F12/00 ,  G06F13/00

Abstract: Classifying memory errors may include accessing data from a location within a memory array of a memory device. The memory array may include at least one bit field to store memory error classification information. One or more memory errors in the data may be determined. One or more memory errors may further be classified. In response to the classifying, memory error classification information may be stored as one or more bit values within the bit field.

公开(公告)号：US09607716B2

公开(公告)日：2017-03-28

申请号：US14248480

申请日：2014-04-09

Applicant: International Business Machines Corporation

Inventor： Charles A. Kilmer ,  Warren E. Maule ,  Saravanan Sethuraman

IPC: G11C11/412 ,  G11C11/413 ,  G11C29/50 ,  G11C29/00 ,  G11C29/02 ,  H01L23/538 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18

CPC classification number: G11C29/50004 ,  G11C29/022 ,  G11C29/025 ,  G11C29/70 ,  G11C29/702 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13188 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014

Abstract: A method for testing a stacked memory device having a plurality of memory chips connected to and arranged on top of a logic chip for a connection defect is disclosed. The method may include testing a memory chip by writing a data value into a first location in the memory chip, reading a data value from the first location, detecting a first bit error and recording a bit number of the first bit error. The method may also include testing the memory chip by writing a data value into a second location in the memory chip, reading a data value from the second location in the memory chip, detecting a second bit error and recording a bit number of the second bit error. The method may also include replacing a connection common to the first and second bit errors with a spare connection.

公开(公告)号：US20170060780A1

公开(公告)日：2017-03-02

申请号：US14841787

申请日：2015-09-01

Applicant: International Business Machines Corporation

Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary ,  Stephen P. Glancy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/0246 ,  G06F21/88 ,  G06F2212/1052 ,  G06F2212/7209

Abstract: Keys are generated at a memory device with a period of time elapsing between generation of each key. A request is received from a memory controller for the most recently generated key. The memory device communicates the first key to the memory controller. Access to nonvolatile memory on the memory device is locked. An unlock command with a second key is received from the memory controller. The memory device determines that the second key matches the first key and unlocks access to the nonvolatile memory in response.

公开(公告)号：US20170060657A1

公开(公告)日：2017-03-02

申请号：US14842917

申请日：2015-09-02

Applicant: International Business Machines Corporation

Inventor： Michael B. Healy ,  Hillery C. Hunter ,  Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule

IPC: G06F11/07

CPC classification number: G06F11/079 ,  G06F11/073 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/1048 ,  G06F11/1068 ,  G11C29/52 ,  G11C2029/0411

Abstract: A correctable memory error may be identified at a first address within a memory device. Based on at least the identifying, a first correctable memory error count may be updated from a first quantity to a second quantity. The second quantity may be determined to exceed or not exceed a threshold. In response to the determining, the first correctable memory error count of the second quantity may be: converted to a third quantity and reported to a host device accordingly, reported to a host device, or not reported to a host device.

Abstract translation: 可以在存储器设备内的第一地址处识别可校正的存储器错误。 基于至少所述识别，可以将第一可校正存储器错误计数从第一数量更新为第二数量。 可以确定第二数量超过或不超过阈值。 响应于确定，第二数量的第一可校正存储器错误计数可以：转换为第三数量并相应地报告给主机设备，报告给主机设备，或者不向主机设备报告。