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    Protective structure
    31.
    发明授权
    Protective structure 有权
    防护结构

    公开(公告)号：US08766415B2

    公开(公告)日：2014-07-01

    申请号：US14011885

    申请日：2013-08-28

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

    IPC: H01L31/075 ,  H01L31/105 ,  H01L31/117

    CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

    Abstract: A protective structure may include: a semiconductor substrate having a doping of a first conductivity type; a semiconductor layer having a doping of a second conductivity type arranged at a surface of the semiconductor substrate; a buried layer having a doping of the second conductivity type arranged in a first region of the semiconductor layer and at the junction between the semiconductor layer and the semiconductor substrate; a first dopant zone having a doping of the first conductivity type arranged in the first region of the semiconductor layer above the buried layer; a second dopant zone having a doping of the second conductivity type arranged in a second region of the semiconductor layer; an electrical insulation arranged between the first region and the second region of the semiconductor layer; and a common connection device for the first dopant zone and the second dopant zone.

    Abstract translation: 保护结构可以包括：具有第一导电类型的掺杂的半导体衬底; 具有布置在所述半导体衬底的表面处的第二导电类型的掺杂的半导体层; 具有布置在所述半导体层的第一区域中以及所述半导体层和所述半导体衬底之间的接合处的掺杂所述第二导电类型的掩埋层; 第一掺杂区，其具有布置在所述半导体层的所述第一区域之上的所述第一导电类型的掺杂; 具有布置在所述半导体层的第二区域中的所述第二导电类型的掺杂的第二掺杂区; 布置在半导体层的第一区域和第二区域之间的电绝缘体; 以及用于第一掺杂区和第二掺杂区的公共连接装置。

    Overvoltage Protection Device with Trench Contact
    32.
    发明公开
    Overvoltage Protection Device with Trench Contact 审中-公开

    公开(公告)号：US20230307388A1

    公开(公告)日：2023-09-28

    申请号：US17702342

    申请日：2022-03-23

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Isabella Goetz ,  Egle Tylaite

    IPC: H01L23/62 ,  H01L27/02

    CPC classification number: H01L23/62 ,  H01L27/0248

    Abstract: An overvoltage protection device includes a semiconductor body including a substrate region disposed beneath an upper surface of the semiconductor body, first and second contact pads disposed over the upper surface of the semiconductor body, a trenched connector formed in the semiconductor body, a vertical voltage blocking device formed in the semiconductor body, wherein the trenched connector includes a trench that is formed in the upper surface of the semiconductor body and extends to the substrate region, and a metal electrode disposed within the trench, wherein the metal electrode forms an electrically conductive connection between the first contact pad and the substrate region, and wherein the voltage blocking device is connected between the second contact pad and the substrate region.

    Electronic device
    33.
    发明授权
    Electronic device 有权

    公开(公告)号：US11127733B2

    公开(公告)日：2021-09-21

    申请号：US16783188

    申请日：2020-02-06

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Stefan Pompl ,  Damian Sojka ,  Katharina Umminger

    IPC: H01L27/02 ,  H01L23/60 ,  H01L21/78 ,  H01L23/538 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L29/74 ,  H02H9/04 ,  H01L27/07

    Abstract: An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

    Method of singulating semiconductor devices using isolation trenches
    37.
    发明授权
    Method of singulating semiconductor devices using isolation trenches 有权
    使用隔离沟槽分割半导体器件的方法

    公开(公告)号：US09543208B2

    公开(公告)日：2017-01-10

    申请号：US14188355

    申请日：2014-02-24

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka ,  Isabella Goetz

    IPC: H01L21/762 ,  H01L21/82 ,  H01L21/765 ,  H01L29/06 ,  H01L21/301

    CPC classification number: H01L21/82 ,  H01L21/76224 ,  H01L21/765 ,  H01L21/78 ,  H01L29/0649

    Abstract: In accordance with an embodiment of the present invention, a method for forming a semiconductor device includes forming a device region in a substrate. The device region extends continuously from one sidewall of the substrate to an opposite sidewall of the substrate. The method further includes forming trenches in the substrate. The trenches divide the device region into active regions. The method also includes singulating the substrate by separating the substrate along the trenches.

    Abstract translation: 根据本发明的实施例，一种用于形成半导体器件的方法包括在衬底中形成器件区域。 器件区域从衬底的一个侧壁连续延伸到衬底的相对侧壁。 该方法还包括在衬底中形成沟槽。 沟槽将设备区域划分为活动区域。 该方法还包括通过沿着沟槽分离衬底来分离衬底。

    Vertically integrated semiconductor device and manufacturing method
    38.
    发明授权
    Vertically integrated semiconductor device and manufacturing method 有权
    垂直集成半导体器件及其制造方法

    公开(公告)号：US09515177B2

    公开(公告)日：2016-12-06

    申请号：US14552567

    申请日：2014-11-25

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka

    IPC: H01L27/00 ,  H01L29/00 ,  H01L29/74 ,  H01L29/66 ,  H01L27/02

    CPC classification number: H01L29/66371 ,  H01L21/28562 ,  H01L27/0251 ,  H01L27/0262 ,  H01L29/7412

    Abstract: A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer disposed over the first semiconducting layer; a third semiconducting layer disposed over the second semiconducting layer; and an electrical bypass coupled between the first semiconducting layer and the second semiconducting layer.

    Abstract translation: 根据各种实施例的垂直集成的半导体器件可以包括：第一半导体层; 设置在所述第一半导体层上的第二半导电层; 设置在所述第二半导体层上的第三半导体层; 以及耦合在所述第一半导体层和所述第二半导体层之间的电旁路。

    Semiconductor Devices and Methods of Formation Thereof
    39.
    发明申请
    Semiconductor Devices and Methods of Formation Thereof 有权
    半导体器件及其形成方法

    公开(公告)号：US20150243561A1

    公开(公告)日：2015-08-27

    申请号：US14188355

    申请日：2014-02-24

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka ,  Isabella Goetz

    IPC: H01L21/82 ,  H01L29/06 ,  H01L21/765

    CPC classification number: H01L21/82 ,  H01L21/76224 ,  H01L21/765 ,  H01L21/78 ,  H01L29/0649

    Abstract: In accordance with an embodiment of the present invention, a method for forming a semiconductor device includes forming a device region in a substrate. The device region extends continuously from one sidewall of the substrate to an opposite sidewall of the substrate. The method further includes forming trenches in the substrate. The trenches divide the device region into active regions. The method also includes singulating the substrate by separating the substrate along the trenches.

    Abstract translation: 根据本发明的实施例，一种用于形成半导体器件的方法包括在衬底中形成器件区域。 器件区域从衬底的一个侧壁连续延伸到衬底的相对侧壁。 该方法还包括在衬底中形成沟槽。 沟槽将设备区域划分为活动区域。 该方法还包括通过沿着沟槽分离衬底来分离衬底。

    METHOD FOR PRODUCING A PROTECTIVE STRUCTURE
    40.
    发明申请
    METHOD FOR PRODUCING A PROTECTIVE STRUCTURE 有权
    生产保护结构的方法

    公开(公告)号：US20140235039A1

    公开(公告)日：2014-08-21

    申请号：US14260301

    申请日：2014-04-24

    Applicant: Infineon Technologies AG

    Inventor： Andre Schmenn ,  Damian Sojka ,  Carsten Ahrens

    IPC: H01L29/66 ,  H01L21/265 ,  H01L21/22

    CPC classification number: H01L27/0255 ,  H01L21/22 ,  H01L21/265 ,  H01L29/66121 ,  H01L29/868

    Abstract: A method for producing a protective structure may include: providing a semiconductor base substrate with a doping of a first conductivity type; producing a first epitaxial layer on the substrate; implanting a dopant of a second conductivity type in a delimited implantation region of the first epitaxial layer; applying a second epitaxial layer with a doping of the second conductivity type on the first epitaxial layer; forming an insulation zone in the second epitaxial layer, such that the second epitaxial layer is subdivided into first and second regions; producing a first dopant zone with a doping of the first conductivity type in the first region above the implantation region; producing a second dopant zone with a doping of the second conductivity type in the second region; outdiffusing the dopant from the implantation region to form a buried layer at the junction between the first epitaxial layer and the first region.

    Abstract translation: 制造保护结构的方法可以包括：提供具有第一导电类型的掺杂的半导体基底衬底; 在衬底上产生第一外延层; 在所述第一外延层的界定的注入区域中注入第二导电类型的掺杂剂; 在所述第一外延层上施加掺杂所述第二导电类型的第二外延层; 在所述第二外延层中形成绝缘区，使得所述第二外延层被细分成第一和第二区域; 在注入区域上方的第一区域中产生掺杂第一导电类型的第一掺杂区; 在所述第二区域中产生掺杂所述第二导电类型的第二掺杂区; 从注入区域向外扩散掺杂剂以在第一外延层和第一区域之间的结处形成掩埋层。

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