公开(公告)号：US20190042498A1

公开(公告)日：2019-02-07

申请号：US15987854

申请日：2018-05-23

Applicant: Intel Corporation

Inventor： Tonia G. MORRIS ,  Bill NALE

IPC: G06F13/16 ,  G06F3/06 ,  G06F9/30

Abstract: A memory subsystem enables per device addressability (PDA) to target configuration commands to one of multiple memory devices that share a select line or buffer devices that share an enable line. The system includes a host and multiple memory devices that can be coupled over a command bus and a data bus. The devices include a configuration or mode register to store a value to indicate whether PDA enumeration is enabled. When enabled, the host can provide an enumeration identifier (ID) command via the command bus with a signal via the data bus to assign an enumeration ID. After assignment of the enumeration ID, the host can send PDA commands via the command bus with the enumeration ID, without a signal on the data bus. Devices only process PDA commands that match their assigned enumeration ID, enabling the setting of device-specific configuration settings without needing to use the data bus on every PDA command.

公开(公告)号：US20180024878A1

公开(公告)日：2018-01-25

申请号：US15724222

申请日：2017-10-03

Applicant: Intel Corporation

Inventor： Debaleena DAS ,  Bill NALE ,  Kuljit S. BAINS ,  John B. HALBERT

IPC: G06F11/10 ,  G06F11/00

CPC classification number: G06F11/1048 ,  G06F11/00 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1084

Abstract: Error correction in a memory subsystem includes a memory device generating internal check bits after performing internal error detection and correction, and providing the internal check bits to the memory controller. The memory device performs internal error detection to detect errors in read data in response to a read request from the memory controller. The memory device selectively performs internal error correction if an error is detected in the read data. The memory device generates check bits indicating an error vector for the read data after performing internal error detection and correction, and provides the check bits with the read data to the memory controller in response to the read request. The memory controller can apply the check bits for error correction external to the memory device.

公开(公告)号：US20160210187A1

公开(公告)日：2016-07-21

申请号：US15080577

申请日：2016-03-24

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  Jonathan C. JASPER ,  Murugasamy K. NACHIMUTHU ,  Jun ZHU ,  Tuan M. QUACH

IPC: G06F11/07

Abstract: Provided are a method and apparatus for performing error handling operations using error signals A first error signal is asserted on an error pin on a bus to signal to a host memory controller that error handling operations are being performed by a memory module controller in response to detecting an error. Error handling operations are performed to return the bus to an initial state in response to detecting the error. A second error signal is asserted on the error pin on the bus to signal that error handling operations have completed and the bus is returned to the initial state.

Abstract translation: 提供了一种用于使用误差信号执行错误处理操作的方法和装置。第一错误信号在总线上的错误引脚上被断言，以向主机存储器控制器通知响应于检测到的存储器模块控制器执行错误处理操作 一个错误。 执行错误处理操作以响应于检测到错误将总线返回到初始状态。 在总线上的错误引脚上断言第二个错误信号，表示错误处理操作已经完成，总线返回初始状态。

公开(公告)号：US20160179742A1

公开(公告)日：2016-06-23

申请号：US15058126

申请日：2016-03-01

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  Jun ZHU ,  Tuan M. QUACH

IPC: G06F13/42 ,  G06F13/16

Abstract: Provided are a method and apparatus for providing a host memory controller write credits for write commands. A host memory controller coupled to a memory module over a bus determines whether a read data packet returned from the memory module indicates at least one write credit and increments a write credit counter in response to determining that the read data packet indicates at least one write credit.

Abstract translation: 提供了一种用于为写入命令提供主机存储器控制器写入信用的方法和装置。 通过总线耦合到存储器模块的主机存储器控制器确定从存储器模块返回的读取数据分组是否指示至少一个写入信用，并响应于确定读取的数据分组指示至少一个写入信用来增加写入信用计数器 。

公开(公告)号：US20160099044A1

公开(公告)日：2016-04-07

申请号：US14967230

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill NALE ,  Jun ZHU ,  Tuan M. QUACH

IPC: G11C11/406 ,  G06F13/16 ,  G06F13/42 ,  G11C7/10 ,  G11C7/22

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module in a first clock cycle. A chip select signal is placed on the bus for the memory module for the first half of the command. A second half of the command is placed on the bus in a second clock cycle following the first clock cycle, wherein the memory module accepts the second half of the command a delay interval from accepting the first half of the command.

Abstract translation: 提供了一种用于存储器模块以多个部分接受命令的方法和装置。 命令的前半部分在第一个时钟周期内放置在内存模块的总线上。 在命令的前半部分，内存模块的总线上放置芯片选择信号。 命令的后半部分在第一时钟周期之后的第二时钟周期中被放置在总线上，其中存储器模块接受命令的后半部分延迟间隔，以接受命令的前半部分。

公开(公告)号：US20160098195A1

公开(公告)日：2016-04-07

申请号：US14967210

申请日：2015-12-11

Applicant: INTEL CORPORATION

Inventor： Bill NALE

IPC: G06F3/06 ,  G06F12/08

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided are a method and apparatus for determining a timing adjustment of output to a host memory controller in a first memory module coupled to a host memory controller and a second memory module over a bus. A determination is made of a timing adjustment based on at least one component in at least one of the first memory module and the second memory module. A timing of output to the host memory controller is adjusted based on the determined timing adjustment to match a timing of output at the second memory module.

Abstract translation: 提供了一种用于确定通过总线耦合到主存储器控制器和第二存储器模块的第一存储器模块中的主机存储器控制器的输出的定时调整的方法和装置。 确定基于第一存储器模块和第二存储器模块中的至少一个中的至少一个组件的定时调整。 基于所确定的定时调整来调整输出到主机存储器控制器的定时，以匹配第二存储器模块处的输出定时。

公开(公告)号：US20240021263A1

公开(公告)日：2024-01-18

申请号：US18373658

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Bill NALE

IPC: G11C29/46 ,  G11C29/44 ,  G11C29/02 ,  G06F11/30 ,  G11C29/00 ,  G06F11/32

CPC classification number: G11C29/46 ,  G11C29/44 ,  G11C29/022 ,  G06F11/3058 ,  G11C29/76 ,  G06F11/326 ,  G06F11/3037 ,  G11C29/021

Abstract: Self-test and repair of memory cells is performed in a memory integrated circuit by two separate processes initiated by a memory controller communicatively coupled to the memory integrated circuit. To ensure that the repair process is completed in the event of an unexpected power failure, a first process is initiated by the memory controller to perform a memory Built-in Self Test (mBIST) in the memory integrated circuit and a second process is initiated by the memory controller after the mBIST has completed to perform repair of faulty memory cells detected during the MBIST process. The memory controller does not initiate the repair process if a power failure has been detected. In addition, a repair time associated with the repair process is selected such that the repair time is sufficient to complete the repair process while power is stable, if a power failure occurs after the repair process has been started.

公开(公告)号：US20230386548A1

公开(公告)日：2023-11-30

申请号：US18213231

申请日：2023-06-22

Applicant: Intel Corporation

Inventor： Bill NALE ,  Christopher E. COX

IPC: G11C11/406 ,  G11C11/4096 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G11C11/4096 ,  G06F3/0673 ,  G06F3/0659 ,  G06F3/0619 ,  G11C11/40618

Abstract: A memory device with internal row hammer mitigation couples to a memory controller. The memory controller or host can assist with row hammer mitigation by sending additional refresh cycles or refresh commands. In response to an extra refresh command the memory device can perform refresh for row hammer mitigation instead of refresh for standard data integrity. The memory controller can keep track of the number of activate commands sent to the memory device, and in response to a threshold number of activate commands, the memory controller sends the additional refresh command. With the extra refresh command the memory device can refresh the potential victim rows of a potential aggressor row, instead of simply refreshing a row that has not been accessed for a period of time.

公开(公告)号：US20220121398A1

公开(公告)日：2022-04-21

申请号：US17561598

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Bill NALE ,  Kuljit S. BAINS

IPC: G06F3/06 ,  G11C11/406

Abstract: A memory device can internally track row address activates for perfect row hammer tracking, incrementing an activate count for each row when an access command is received for a row. Instead of incrementing the count for each activate, the memory controller can indicate a number greater than one for the memory device to increment the count, and then indicate not to increment the count for subsequent accesses up to the number indicated. The memory controller can determine whether the row address of an activate command is one of N recent row addresses that received the access command. The memory controller can indicate an increment of zero if the row address is one of the N recent addresses, and indicate an increment of a number higher than one if the row address is not one of the N recent addresses.

公开(公告)号：US20210365316A1

公开(公告)日：2021-11-25

申请号：US17339754

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： Bill NALE ,  Kuljit S. BAINS ,  Lawrence BLANKENBECKLER ,  Ronald ANDERSON ,  Jongwon LEE

IPC: G06F11/10 ,  G11C11/406

Abstract: A memory chip is described. The memory chip includes storage cells along a row of the memory chip's storage cell array to store a count value of the row's activations and error correction code (ECC) information to protect the count value. The memory chip includes ECC read logic circuitry to correct an error in the count value. The memory chip includes a comparator to compare the count value against a threshold. The memory chip includes circuitry to increment the count value if the count value is deemed not to have reached the threshold and ECC write logic circuitry to determine new ECC information for the incremented count value, and write driver circuitry to write the incremented count value and the new ECC information into the storage cells. The memory chip includes circuitry to cause the row to be refreshed if the count value is deemed to have reached the threshold.