中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

47 records (took 0.014 seconds)

    ELECTRICAL INTERCONNECTIONS WITH IMPROVED COMPLIANCE DUE TO STRESS RELAXATION AND METHOD OF MAKING
    32.
    发明申请
    ELECTRICAL INTERCONNECTIONS WITH IMPROVED COMPLIANCE DUE TO STRESS RELAXATION AND METHOD OF MAKING 审中-公开

    公开(公告)号：US20190393129A1

    公开(公告)日：2019-12-26

    申请号：US16540177

    申请日：2019-08-14

    Applicant: Intel Corporation

    Inventor： Siddharth K. Alur ,  Sri Chaitra Jyotsna Chavali

    IPC: H01L23/373 ,  H01L23/498 ,  H01L23/367 ,  H01L21/48

    Abstract: According to various embodiments of the present disclosure, an electrically conductive pillar having a substrate is disclosed. The electrically conductive pillar can comprise a first portion, second portion and a third portion. The first portion and/or third portion can be formed of an electrically conductive material that can be the same or different. The second portion can be intermediate and abut both the first portion and the third portion. The second portion can comprise a solder element formed of a second electrically conductive material that differs from the electrically conductive material and has a second stiffness less than a stiffness of the electrically conductive material.

    Embedded die architecture and method of making
    35.
    发明授权
    Embedded die architecture and method of making 有权

    公开(公告)号：US12224245B2

    公开(公告)日：2025-02-11

    申请号：US16724907

    申请日：2019-12-23

    Applicant: Intel Corporation

    Inventor： Sanka Ganesan ,  Robert L. Sankman ,  Sri Chaitra Jyotsna Chavali

    IPC: H01L23/538 ,  H01L21/768 ,  H01L23/498

    Abstract: Various examples provide a semiconductor package. The semiconductor package includes a substrate having first and second opposed substantially planar major surfaces extending in an x-y direction. The package further includes a bridge die having third and fourth opposed substantially planar major surfaces extending in the x-y direction. The third substantially planar major surface of the bridge die is in direct contact with the second substantially planar major surface of the substrate. The semiconductor package further includes a through silicon via extending in a z-direction through the first substantially planar major surface of the substrate and the fourth substantially planar major surface of the bridge die. The semiconductor package further includes a power source coupled to the through silicon via, a first electronic component electronically coupled to the bridge die, and a second electronic component electronically coupled to the bridge die. The semiconductor package further includes an overmold at least partially encasing the first electronic component, second electronic component, and the bridge die.

    HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES
    36.
    发明公开
    HIGH DENSITY ORGANIC INTERCONNECT STRUCTURES 审中-公开

    公开(公告)号：US20240355641A1

    公开(公告)日：2024-10-24

    申请号：US18761453

    申请日：2024-07-02

    Applicant: Intel Corporation

    Inventor： Sri Chaitra Jyotsna Chavali ,  Siddharth K. Alur ,  Lilia May ,  Amanda E. Shuckman

    IPC: H01L21/48 ,  H01L23/498

    CPC classification number: H01L21/4857 ,  H01L23/49822 ,  H01L23/49827

    Abstract: Generally discussed herein are systems, devices, and methods that include an organic high-density interconnect structure and techniques for making the same. According to an example a method can include forming one or more low-density buildup layers on a core, conductive interconnect material of the one or more low-density buildup layers electrically and mechanically connected to conductive interconnect material of the core, forming one or more high-density buildup layers on an exposed low-density buildup layer of the one or more low-density buildup layers, conductive interconnect material of the high-density buildup layers electrically and mechanically connected to the conductive interconnect material of the one or more low-density buildup layers, and forming another low-density buildup layer on and around an exposed high-density buildup layer of the one or more high-density buildup layers.

Patent Agency Ranking