公开(公告)号：US20210391263A1

公开(公告)日：2021-12-16

申请号：US16902958

申请日：2020-06-16

Applicant: Intel Corporation

Inventor： Bai Nie ,  Gang Duan ,  Omkar G. Karhade ,  Nitin A. Deshpande ,  Yikang Deng ,  Wei-Lun Jen ,  Tarek A. Ibrahim ,  Sri Ranga Sai Boyapati ,  Robert Alan May ,  Yosuke Kanaoka ,  Robin Shea McRee ,  Rahul N. Manepalli

IPC: H01L23/538 ,  H01L21/48

Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.

公开(公告)号：US12249584B2

公开(公告)日：2025-03-11

申请号：US17323194

申请日：2021-05-18

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Benjamin T. Duong ,  Srinivas V. Pietambaram ,  Tarek A. Ibrahim

IPC: H01L23/64 ,  H01F3/10 ,  H01L21/768 ,  H01L23/538 ,  H01L25/065 ,  H01L49/02

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die in a first dielectric layer; a magnetic core inductor, having a first surface and an opposing second surface, in the first dielectric layer, including a first conductive pillar, having a first end at the first surface of the magnetic core inductor and an opposing second end at the second surface, at least partially surrounded by a magnetic material that extends at least partially along a thickness of the first conductive pillar from the second end and tapers towards the first end; and a second conductive pillar coupled to the first conductive pillar; and a second die in a second dielectric layer on the first dielectric layer coupled to the second surface of the magnetic core inductor.

公开(公告)号：US20250004225A1

公开(公告)日：2025-01-02

申请号：US18345106

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  David Shia ,  Tarek A. Ibrahim ,  Yuxin Fang

IPC: G02B6/42

Abstract: Technologies for substrate features for a pluggable optical connectors in an integrated circuit package are disclosed. In the illustrative embodiment, a substrate includes a cavity cut through a substrate of the integrated circuit package. Sidewalls of the cavity establish coarse lateral alignment features for an optical plug. The optical plug and optical socket include additional alignment features to more precisely align optical fibers in the optical plug to an optical interposer mounted on the substrate. The cavity cut through the substrate may also include indents that can mate with protrusions of the optical plug to retain the optical plug. The optical interposer may be mounted on a recessed shelf in the substrate.

公开(公告)号：US12181710B2

公开(公告)日：2024-12-31

申请号：US17237375

申请日：2021-04-22

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Xiaoqian Li ,  Tarek A. Ibrahim ,  Ravindranath Vithal Mahajan ,  Nitin A. Deshpande

IPC: G02B6/122 ,  G02B6/12

Abstract: Photonic packages and device assemblies that include photonic integrated circuits (PICs) coupled to optical lenses on lateral sides of the PICs. An example photonic package comprises a package support, an integrated circuit (IC), an insulating material, a PIC having an active side and a lateral side substantially perpendicular to the active side. At least one optical structure is on the active side. A substantial portion of the active side is in contact with the insulating material, and the PIC is electrically coupled to the package support and to the IC. The photonic package further includes an optical lens coupled to the PIC on the lateral side. In some embodiments, the photonic package further includes an interposer between the PIC or the IC and the package support.

公开(公告)号：US20240113049A1

公开(公告)日：2024-04-04

申请号：US17937474

申请日：2022-10-03

Applicant: Intel Corporation

Inventor： Kristof Kuwawi Darmawikarta ,  Cemil S. Geyik ,  Kemal Aygun ,  Tarek A. Ibrahim ,  Wei-Lun Jen ,  Zhiguo Qian ,  Dilan Seneviratne

IPC: H01L23/66 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L23/66 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5386 ,  H01L21/486 ,  H01L2223/6616 ,  H01L2223/6627

Abstract: Embodiments of a microelectronic assembly that includes: a package substrate, comprising buildup layers of an organic dielectric material and a plurality of layers of conductive traces in the organic dielectric material, the package substrate having a first surface and a second surface opposite the first surface; and a plurality of integrated circuit (IC) dies coupled to the package substrate on the first side. The plurality of layers of conductive traces comprises a pair of stripline traces or microstrips in one of the layers, the stripline traces or microstrips are surrounded by air gap structures in the organic dielectric material, and the air gap structures are exposed on the first surface.

公开(公告)号：US20240027706A1

公开(公告)日：2024-01-25

申请号：US17871473

申请日：2022-07-22

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Eric J. M. Moret ,  Tarek A. Ibrahim ,  David Shia ,  Nicholas D. Psaila ,  Russell Childs

IPC: G02B6/42 ,  G02B6/43

CPC classification number: G02B6/4249 ,  G02B6/43 ,  G02B6/4214 ,  G02B6/4292

Abstract: In one embodiment, an integrated circuit device includes a substrate, an electronic integrated circuit (EIC), a photonics integrated circuit (PIC) electrically coupled to the EIC, and a glass block at least partially in a cavity defined by the substrate and at an end of the substrate. The glass block defines an optical path with one or more optical elements to direct light between the PIC and a fiber array unit (FAU) when attached to the glass block.

公开(公告)号：US11817390B2

公开(公告)日：2023-11-14

申请号：US18090795

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Sanka Ganesan ,  Ram Viswanath ,  Xavier Francois Brun ,  Tarek A. Ibrahim ,  Jason M. Gamba ,  Manish Dubey ,  Robert Alan May

IPC: H01L23/538 ,  H01L23/367 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5381 ,  H01L23/3185 ,  H01L23/367 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L2224/16227

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.

公开(公告)号：US20230317619A1

公开(公告)日：2023-10-05

申请号：US17711978

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Ravindranath V. Mahajan ,  Srikant Nekkanty ,  Srinivas V. Pietambaram ,  Veronica Strong ,  Xiao Lu ,  Tarek A. Ibrahim ,  Karumbu Nathan Meyyappan ,  Dingying Xu ,  Kristof Darmawikarta

IPC: H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5381 ,  H01L21/486 ,  H01L23/5384

Abstract: A microelectronic structure, a semiconductor package including the same, and a method of forming same. The microelectronic structures includes: a substrate defining a cavity therein; a bridge die within the cavity, the bridge die to electrically couple a pair of dies to be provided on a surface of the substrate; an electrical coupling layer between a top surface of the cavity and a bottom surface of the bridge die. The electrical coupling layer includes: a non-conductive component including a die bonding film and defining holes therein; and electrically conductive structures in the holes, the electrically conductive structures electrically coupling the substrate with the bridge die.

公开(公告)号：US20230093186A1

公开(公告)日：2023-03-23

申请号：US17479871

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Tarek A. Ibrahim ,  Rahul N. Manepalli ,  Sairam Agraharam ,  Xiaoxuan Sun

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a semiconductor device. In selected examples, the semiconductor device may include two semiconductor dies, a redistribution layer, an interconnect bridge coupled between the two semiconductor dies and located vertically between the two semiconductor dies and the redistribution layer, and a metallic connection passing through the redistribution layer and coupled to one or more of the two semiconductor dies in a solder-free connection.

公开(公告)号：US20230077633A1

公开(公告)日：2023-03-16

申请号：US17476080

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Changhua Liu ,  Pooya Tadayon ,  John Heck ,  Eric J. Moret ,  Tarek A. Ibrahim ,  Zhichao Zhang ,  Jeremy D Ecton

IPC: G02B6/42

Abstract: An electronic device comprises a photonic integrated circuit (PIC) including at least one waveguide, an emitting lens disposed on the PIC to emit light from the at least one waveguide in a direction substantially parallel to a first surface of the PIC, and an optical element disposed on the PIC and having a reflective surface configured to direct light emitted from the emitting lens in a direction away from the first surface of the PIC.