公开(公告)号：US09299928B2

公开(公告)日：2016-03-29

申请号：US14625867

申请日：2015-02-19

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: G11C11/00 ,  G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1616

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

公开(公告)号：US09184383B2

公开(公告)日：2015-11-10

申请号：US14156762

申请日：2014-01-16

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

Abstract translation: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中，界面层结构包括钝化区域，界面耦合区域和/或可变电阻层接口区域，其被配置为调整非易失性存储器件的性能，例如降低形成 器件的开关电流并降低器件的成型电压，并降低从一个成形器件到另一个器件的性能变化。

公开(公告)号：US09178148B2

公开(公告)日：2015-11-03

申请号：US14636421

申请日：2015-03-03

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Imran Hashim ,  Ryan C. Clarke ,  Nan Lu ,  Tim Minvielle ,  Takeshi Yamaguchi

IPC: H01L45/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: H01L45/146 ,  G11C11/56 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/77 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1253

Abstract: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

公开(公告)号：US20150170837A1

公开(公告)日：2015-06-18

申请号：US14133496

申请日：2013-12-18

Applicant: Intermolecular, Inc.

Inventor： Sucharita Madhukar ,  Nobumichi Fuchigami ,  Imran Hashim ,  Wen Wu

IPC: H01G4/008 ,  H01G4/10

CPC classification number: H01G4/008 ,  H01G4/10 ,  Y10T29/435

Abstract: A hafnium oxide-aluminum oxide-hafnium oxide (HAH) based multilayer stack is used as the dielectric material in the formation of decoupling capacitors employed in microelectronic logic circuits. In some embodiments, the thickness of the aluminum oxide layer in the HAH multilayer stack varies between 0.1 nm and 1 nm. In some embodiments, the thickness of the two hafnium oxide layers varies between about 3.0 nm and 4.5 nm.

Abstract translation: 在形成微电子逻辑电路中使用的去耦电容器时，使用基于氧化铪 - 氧化铪 - 氧化铪氧化物（HAH）的多层叠层作为介电材料。 在一些实施例中，HAH多层叠层中的氧化铝层的厚度在0.1nm和1nm之间变化。 在一些实施例中，两个氧化铪层的厚度在约3.0nm和4.5nm之间变化。

公开(公告)号：US20150162530A1

公开(公告)日：2015-06-11

申请号：US14625867

申请日：2015-02-19

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1253 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/56 ,  G11C2213/76 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/148 ,  H01L45/1616

Abstract: Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., “set” and “reset” steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

Abstract translation: 本发明的实施例通常包括一种形成非易失性存储器件的方法，该非易失性存储器件包含由于添加限定在其中的限流部件而具有改进的器件切换性能和寿命的电阻式开关存储元件。 在一个实施例中，限流部件包括至少一层电阻材料，其被配置为提高所形成的电阻式开关存储元件的开关性能和寿命。 所形成的限流层或电阻层的电性能被配置为在逻辑状态编程步骤（即“设定”和“复位”步骤）期间通过添加固定的串联电阻来降低通过可变电阻层的电流 在形成在非易失性存储器件中的电阻式开关存储元件中。 通常，电阻式开关存储器元件可以形成为可用于各种电子设备（例如数码相机，移动电话，手持式计算机和音乐播放器）的大容量非易失性存储器集成电路的一部分。

公开(公告)号：US08975727B2

公开(公告)日：2015-03-10

申请号：US13721310

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Yun Wang ,  Tony P. Chiang ,  Imran Hashim ,  Tim Minvielle ,  Dipankar Pramanik ,  Takeshi Yamaguchi

IPC: H01L29/8605 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/12 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146

Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.

Abstract translation: 提供了一种结合到具有改进的性能和寿命的电阻式开关存储单元中的电阻器结构。 电阻器结构可以是设计成减小流过存储器单元的最大电流的两端结构。 还提供了一种用于制造这种存储单元的方法。 该方法包括沉积电阻器结构并沉积存储单元的电阻式开关存储单元的可变电阻层，其中电阻器结构与可变电阻层串联布置以限制存储单元的开关电流。 电阻器结构的结合对于获得满足各种类型的存储器单元的开关规范的期望的开关电流水平是非常有用的。 存储单元可以形成为可用于各种电子设备的大容量非易失性存储器集成电路的一部分。

公开(公告)号：US08969169B1

公开(公告)日：2015-03-03

申请号：US14033326

申请日：2013-09-20

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Hanhong Chen ,  David Chi ,  Imran Hashim ,  Mitsuhiro Horikawa ,  Sandra G. Malhotra

IPC: H01L21/00 ,  H01L49/02

CPC classification number: H01L28/56 ,  H01L27/108 ,  H01L27/1085 ,  H01L28/40 ,  H01L28/75 ,  H01L28/82

Abstract: A method for forming a capacitor stack includes forming a first bottom electrode layer including a conductive metal nitride material. A second bottom electrode layer is formed above the first bottom electrode layer. The second bottom electrode layer includes a conductive metal oxide material, wherein the crystal structure of the conductive metal oxide material promotes a desired high-k crystal phase of a subsequently deposited dielectric layer. A dielectric layer is formed above the second bottom electrode layer. Optionally, an oxygen-rich metal oxide layer is formed above the dielectric layer. Optionally, a third top electrode layer is formed above the oxygen-rich metal oxide layer. The third top electrode layer includes a conductive metal oxide material. A fourth top electrode layer is formed above the third top electrode layer. The fourth top electrode layer includes a conductive metal nitride material.

Abstract translation: 形成电容器堆叠的方法包括形成包括导电金属氮化物材料的第一底部电极层。 在第一底部电极层的上方形成第二底部电极层。 第二底部电极层包括导电金属氧化物材料，其中导电金属氧化物材料的晶体结构促进随后沉积的介电层的期望的高k结晶相。 在第二底部电极层的上方形成电介质层。 任选地，在介电层上方形成富氧金属氧化物层。 可选地，在富氧金属氧化物层的上方形成第三上电极层。 第三顶部电极层包括导电金属氧化物材料。 第四上电极层形成在第三顶电极层的上方。 第四顶部电极层包括导电金属氮化物材料。

公开(公告)号：US20140363920A1

公开(公告)日：2014-12-11

申请号：US14466695

申请日：2014-08-22

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Zhendong Hong ,  Vidyut Gopal ,  Imran Hashim ,  Randall J. Higuchi ,  Tim Minvielle ,  Hieu Pham ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack which contains at least one hard metal oxide film (e.g., metal is completely oxidized or substantially oxidized) and at least one soft metal oxide film (e.g., metal is less oxidized than hard metal oxide). The soft metal oxide film is less electrically resistive than the hard metal oxide film since the soft metal oxide film is less oxidized or more metallic than the hard metal oxide film. In one example, the hard metal oxide film is formed by an ALD process utilizing ozone as the oxidizing agent while the soft metal oxide film is formed by another ALD process utilizing water vapor as the oxidizing agent.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其包含至少一个硬金属氧化物膜（例如，金属被完全氧化或基本上被氧化 ）和至少一种软金属氧化物膜（例如，金属比硬金属氧化物氧化较少）。 由于软金属氧化物膜比硬金属氧化物膜氧化得更少或更金属，所以软金属氧化物膜的电阻小于硬金属氧化物膜。 在一个实例中，通过利用臭氧作为氧化剂的ALD工艺形成硬质金属氧化物膜，而通过利用水蒸汽作为氧化剂的另一ALD工艺形成软金属氧化物膜。

公开(公告)号：US08901708B2

公开(公告)日：2014-12-02

申请号：US13675971

申请日：2012-11-13

Applicant: Intermolecular, Inc.

Inventor： Imran Hashim ,  Hanhong Chen ,  Tony Chiang ,  Indranil De ,  Nobumichi Fuchigami ,  Edward Haywood ,  Pragati Kumar ,  Sandra Malhotra ,  Sunil Shanker

IPC: H01L21/02 ,  H01L49/02 ,  C23C16/40 ,  C23C16/455 ,  H01L21/314 ,  H01L21/316 ,  H01L27/108

CPC classification number: H01L28/65 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02697 ,  H01L21/3141 ,  H01L21/31604 ,  H01L27/10852 ,  H01L28/40

Abstract: This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.

公开(公告)号：US08860002B2

公开(公告)日：2014-10-14

申请号：US13721450

申请日：2012-12-20

Applicant: Intermolecular Inc. ,  Kabushiki Kaisha Toshiba ,  SanDisk 3D LLC

Inventor： Mihir Tendulkar ,  Imran Hashim ,  Tim Minvielle ,  Yun Wang ,  Takeshi Yamaguchi

IPC: H01L45/00

CPC classification number: H01L45/1253 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Provided are ReRAM cells, each having at least one interface between an electrode and a resistive switching layers with a maximum field value of less than 0.25. The electrode materials forming such interfaces include tantalum nitrides doped with lanthanum, aluminum, erbium yttrium, or terbium (e.g., TaX(Dopant)YN, where X is at least about 0.95). The electrode materials have low work functions (e.g., less than about 4.5 eV). At the same time, the resistive switching materials have high relative dielectric permittivities (e.g., greater than about 30) and high electron affinities (greater than about for 3.5 eV). Niobium oxide is one example of a suitable resistive switching material. Another electrode interfacing the resistive switching layer may have different characteristics and, in some embodiments, may be an inert electrode.

Abstract translation: 提供的是ReRAM单元，每个单元在电极和电阻切换层之间具有至少一个界面，其最大场值小于0.25。 形成这种界面的电极材料包括掺杂有镧，铝，铒钇或铽的钽氮化物（例如TaX（掺杂剂）YN，其中X为至少约0.95）。 电极材料具有低功函数（例如小于约4.5eV）。 同时，电阻式开关材料具有较高的相对介电常数（例如大于约30）和高电子亲和力（大于3.5eV）。 氧化铌是合适的电阻式开关材料的一个例子。 连接电阻式开关层的另一电极可以具有不同的特性，并且在一些实施例中可以是惰性电极。