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87 条记录 (耗时 0.039 秒)

    Recognition via high-dimensional data classification
    31.
    发明授权
    Recognition via high-dimensional data classification 有权
    通过高维数据分类识别

    公开(公告)号：US08406525B2

    公开(公告)日：2013-03-26

    申请号：US12865639

    申请日：2009-01-29

    申请人： Yi Ma ,  Allen Yang Yang ,  John Norbert Wright ,  Andrew William Wagner

    发明人： Yi Ma ,  Allen Yang Yang ,  John Norbert Wright ,  Andrew William Wagner

    IPC分类号： G06K9/66

    CPC分类号： G06K9/00275 ,  G06K9/6232 ,  G06K9/627

    摘要： A method is disclosed for recognition of high-dimensional data in the presence of occlusion, including: receiving a target data that includes an occlusion and is of an unknown class, wherein the target data includes a known object; sampling a plurality of training data files comprising a plurality of distinct classes of the same object as that of the target data; and identifying the class of the target data through linear superposition of the sampled training data files using l1 minimization, wherein a linear superposition with a sparsest number of coefficients is used to identify the class of the target data.

    摘要翻译： 公开了一种用于在存在遮挡的情况下识别高维数据的方法，包括：接收包括闭塞并且是未知类的目标数据，其中所述目标数据包括已知对象; 对包含与所述目标数据相同的对象的多个不同类别的多个训练数据文件进行采样; 以及使用l1最小化通过采样的训练数据文件的线性叠加来识别目标数据的类别，其中使用具有最少数量的系数的线性叠加来标识目标数据的类别。

    Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices
    32.
    发明授权
    Integrated scheme for forming inter-poly dielectrics for non-volatile memory devices 有权
    用于形成用于非易失性存储器件的多晶硅电介质的集成方案

    公开(公告)号：US07910446B2

    公开(公告)日：2011-03-22

    申请号：US12163542

    申请日：2008-06-27

    申请人： Yi Ma ,  Shreyas Kher ,  Khaled Ahmed

    发明人： Yi Ma ,  Shreyas Kher ,  Khaled Ahmed

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42324

    摘要： Electronic devices and methods for forming electronic devices that allow for a reduction in device dimensions while also maintaining or reducing leakage current for non-volatile memory devices are provided. In one embodiment, a method of fabricating a non-volatile memory device is provided. The method comprises depositing a floating gate polysilicon layer on a substrate, forming a silicon oxide layer on the floating gate polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a high-k dielectric material layer on the first silicon oxynitride layer, depositing a second silicon oxynitride on the high-k dielectric material, and forming a control gate polysilicon layer on the second silicon oxynitride layer. In one embodiment, the high-k dielectric material layer comprises hafnium silicon oxynitride.

    摘要翻译： 提供了用于形成电子器件的电子器件和方法，其允许减小器件尺寸，同时还保持或减少用于非易失性存储器件的漏电流。 在一个实施例中，提供了一种制造非易失性存储器件的方法。 该方法包括在衬底上沉积浮栅多晶硅层，在浮栅多晶硅层上形成氧化硅层，在氧化硅层上沉积第一氮氧化硅层，在第一氮氧化硅上沉积高k电介质材料层 在所述高k电介质材料上沉积第二氮氧化硅，以及在所述第二氮氧化硅层上形成控制栅极多晶硅层。 在一个实施例中，高k电介质材料层包括铪硅氮氧化物。

    METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SMOOT SIDEWALLS AND ROUNDED TOP CORNERS AND EDGES
    34.
    发明申请
    METHODS FOR FABRICATING MEMORY CELLS HAVING FIN STRUCTURES WITH SMOOT SIDEWALLS AND ROUNDED TOP CORNERS AND EDGES 有权
    用于制作具有SMOOT边框和圆顶顶角和边缘的精细结构的记忆细胞的方法

    公开(公告)号：US20090269918A1

    公开(公告)日：2009-10-29

    申请号：US12111122

    申请日：2008-04-28

    申请人： Yi Ma ,  Robert Bertram Ogle

    发明人： Yi Ma ,  Robert Bertram Ogle

    IPC分类号： H01L21/28 ,  H01L21/311

    CPC分类号： H01L21/324 ,  H01L21/3247 ,  H01L27/11568 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/7854 ,  H01L29/792

    摘要： Methods for fabricating a semiconductor FIN structure with smooth sidewalls and rounded top corners and edges is disclosed. A method includes forming a plurality of semiconductor FIN structures. A sacrificial oxide layer is formed on the top surface and the sidewall surfaces of the plurality of semiconductor FIN structures for rounding the corners and edges between the top surfaces and the sidewall surfaces of the plurality of semiconductor FIN structures. The sacrificial oxide layer is removed with a high selectivity oxide etchant. The plurality of semiconductor FIN structures are annealed in a hydrogen environment. A tunnel oxide is formed over the plurality of semiconductor FIN structures.

    摘要翻译： 公开了制造具有平滑侧壁和圆角顶角和边缘的半导体FIN结构的方法。 一种方法包括形成多个半导体FIN结构。 在多个半导体FIN结构的顶表面和侧壁表面上形成牺牲氧化物层，用于使多个半导体FIN结构的顶表面和侧壁表面之间的角和边缘倒圆。 用高选择性氧化物蚀刻剂除去牺牲氧化物层。 多个半导体FIN结构在氢环境中退火。 在多个半导体FIN结构上形成隧道氧化物。

    HETERO-STRUCTURE VARIABLE SILICON RICHNESS NITRIDE FOR MLC FLASH MEMORY DEVICE
    35.
    发明申请
    HETERO-STRUCTURE VARIABLE SILICON RICHNESS NITRIDE FOR MLC FLASH MEMORY DEVICE 失效
    用于MLC闪存存储器件的异质结构可变硅纳米氮

    公开(公告)号：US20090152617A1

    公开(公告)日：2009-06-18

    申请号：US11957787

    申请日：2007-12-17

    申请人： Yi Ma ,  Robert Ogle

    发明人： Yi Ma ,  Robert Ogle

    IPC分类号： H01L29/792 ,  H01L21/31

    CPC分类号： H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/7923

    摘要： Charge storage stacks containing hetero-structure variable silicon richness nitride for memory cells and methods for making the charge storage stacks are provided. The charge storage stack can contain a first insulating layer on a semiconductor substrate; n charge storage layers comprising silicon-rich silicon nitride on the first insulating layer, wherein numbers of the charge storage layers increase from the bottom to the top and a k-value of an n-1th charge storage layer is higher than a k-value of an nth charge storage layer; n-1 dielectric layers comprising substantially stoichiometric silicon nitride between each of the n charge storage layers; and a second insulating layer on the nth charge storage layers.

    摘要翻译： 提供了包含用于存储单元的异质结构可变富硅氮化物的电荷存储堆，以及用于制造电荷存储堆的方法。 电荷存储堆可以包含半导体衬底上的第一绝缘层; n在第一绝缘层上形成包括富硅氮化物的存储层，其中电荷存储层的数量从底部增加到顶部，并且第n-1个电荷存储层的k值高于k值 的第n电荷存储层; n-1个电介质层，其在n个电荷存储层中的每一个之间包含基本上化学计量的氮化硅; 以及第n电荷存储层上的第二绝缘层。

    INTEGRATED CIRCUIT FABRICATION PROCESS FOR A HIGH MELTING TEMPERATURE SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION
    36.
    发明申请
    INTEGRATED CIRCUIT FABRICATION PROCESS FOR A HIGH MELTING TEMPERATURE SILICIDE WITH MINIMAL POST-LASER ANNEALING DOPANT DEACTIVATION 审中-公开
    用于具有最小激光退火猝死活性的高熔点温度硅胶的集成电路制造工艺

    公开(公告)号：US20090042353A1

    公开(公告)日：2009-02-12

    申请号：US11836299

    申请日：2007-08-09

    申请人： Yi Ma ,  Philip Allan Kraus ,  Christopher Sean Olsen ,  Khaled Z. Ahmed ,  Abhilash J. Mayur

    发明人： Yi Ma ,  Philip Allan Kraus ,  Christopher Sean Olsen ,  Khaled Z. Ahmed ,  Abhilash J. Mayur

    IPC分类号： H01L21/331

    CPC分类号： B23K26/0738 ,  B23K26/082 ,  B23K26/0876 ,  H01L21/268 ,  H01L29/665

    摘要： Post-laser annealing dopant deactivation is minimized by performing certain silicide formation process steps prior to laser annealing. A base metal layer of nickel is deposited on the source-drain regions and the gate electrode, followed by deposition of an overlying layer of a metal having a higher melting temperature than nickel. Thereafter, a rapid thermal process is performed to heat the substrate sufficiently to form metal silicide contacts at the top surfaces of the source-drain regions and of the gate electrode. The method further includes removing the remainder of the metal-containing layer and then depositing an optical absorber layer over the substrate prior to laser annealing.

    摘要翻译： 通过在激光退火之前执行特定的硅化物形成工艺步骤，使激光后退火掺杂剂失活最小化。 在源 - 漏区和栅电极上沉积镍的贱金属层，然后沉积具有比镍更高的熔融温度的金属的上覆层。 此后，进行快速热处理以充分加热衬底，以在源极 - 漏极区域和栅电极的顶表面处形成金属硅化物接触。 该方法还包括去除剩余的含金属层，然后在激光退火之前在衬底上沉积光吸收层。

    Gate dielectric structure for reducing boron penetration and current leakage
    37.
    发明授权
    Gate dielectric structure for reducing boron penetration and current leakage 失效
    用于减少硼渗透和电流泄漏的栅介质结构

    公开(公告)号：US07081419B2

    公开(公告)日：2006-07-25

    申请号：US10847789

    申请日：2004-05-18

    申请人： Yuan Chen ,  Feng Li ,  Yi Ma ,  Kurt G. Steiner

    发明人： Yuan Chen ,  Feng Li ,  Yi Ma ,  Kurt G. Steiner

    IPC分类号： H01L21/31

    CPC分类号： H01L21/28202 ,  H01L29/513

    摘要： The present invention provides a semiconductor device capable of substantially retarding boron penetration within the semiconductor device and a method of manufacture therefor. In the present invention the semiconductor device includes a gate dielectric located over a substrate of a semiconductor wafer, wherein the gate dielectric includes a nitrided layer and a dielectric layer. The present invention further includes a nitrided transition region located between the dielectric layer and the nitrided layer and a gate located over the gate dielectric.

    摘要翻译： 本发明提供一种能够显着延迟半导体器件内的硼渗透的半导体器件及其制造方法。 在本发明中，半导体器件包括位于半导体晶片的衬底之上的栅极电介质，其中栅极电介质包括氮化层和电介质层。 本发明还包括位于介电层和氮化层之间的氮化过渡区域和位于栅极电介质上方的栅极。

    Vapor deposition of hafnium silicate materials with tris(dimethylamino)silane
    39.
    发明申请
    Vapor deposition of hafnium silicate materials with tris(dimethylamino)silane 审中-公开
    硅酸铪材料与三（二甲基氨基）硅烷的蒸汽沉积

    公开(公告)号：US20060062917A1

    公开(公告)日：2006-03-23

    申请号：US11223896

    申请日：2005-09-09

    申请人： Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

    发明人： Shankar Muthukrishnan ,  Tejal Goyani ,  Rahul Sharangpani ,  Shreyas Kher ,  Pravin Narwankar ,  Khaled Ahmed ,  Yi Ma

    IPC分类号： C23C16/00

    CPC分类号： C23C16/308 ,  C23C16/401 ,  C23C16/56

    摘要： In one embodiment, a method for forming a morphologically stable dielectric material is provided which includes exposing a substrate to a hafnium precursor, a silicon precursor and an oxidizing gas to form hafnium silicate material during a chemical vapor deposition (CVD) process and subsequently and optionally exposing the substrate to a post deposition anneal, a nitridation process and a thermal annealing process. In some examples, the hafnium and silicon precursors used during a metal-organic CVD (MOCVD) process are alkylamino compounds, such as tetrakis(diethylamino)hafnium (TDEAH) and tris(dimethylamino)silane (Tris-DMAS). In another embodiment, other metal precursors may be used to form a variety of metal silicates containing tantalum, titanium, aluminum, zirconium, lanthanum or combinations thereof.

    摘要翻译： 在一个实施方案中，提供了一种用于形成形态稳定的电介质材料的方法，其包括在化学气相沉积（CVD）工艺期间将衬底暴露于铪前体，硅前体和氧化气体以形成硅酸铪材料，随后和任选地 将衬底暴露于后沉积退火，氮化工艺和热退火工艺。 在一些实例中，在金属 - 有机CVD（MOCVD）方法中使用的铪和硅前体是烷基氨基化合物，例如四（二乙基氨基）铪（TDEAH）和三（二甲氨基）硅烷（Tris-DMAS）。 在另一个实施方案中，其它金属前体可用于形成含有钽，钛，铝，锆，镧或其组合的各种金属硅酸盐。