公开(公告)号：US6091660A

公开(公告)日：2000-07-18

申请号：US376468

申请日：1999-08-18

申请人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

发明人： Toshio Sasaki ,  Yuji Tanaka ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka ,  Jun Sato ,  Takashi Miyamoto ,  Mariko Ohtsuka ,  Satoru Nakanishi ,  Kazushige Ayukawa ,  Takao Watanabe

IPC分类号： G11C11/401 ,  G11C8/00 ,  G11C8/12 ,  G11C11/407

CPC分类号： G11C8/12

摘要： A RAM mounted so as to mix with logic circuits has a plurality of memory mats and one control circuit provided for the plurality of memory mats. Arithmetic circuits for respectively performing +1 or -1 arithmetic operations are respectively provided so as to correspond to the respective memory mats and are electrically connected in cascade form. An input terminal of the initial-stage arithmetic circuit is supplied with address-setting fixed address signals. Input signals supplied to the next and subsequent arithmetic circuits or signals outputted therefrom are defined as own-assigned address signals (those assigned to the corresponding memory mats). A comparator provided in association with each arithmetic circuit referred to above makes comparisons for coincidence between the address signals and address signals input upon memory access. The corresponding memory mat is selected based on the resultant coincidence signal.

摘要翻译： 安装成与逻辑电路混合的RAM具有多个存储器垫和为多个存储器垫提供的一个控制电路。 分别提供用于分别执行+1或-1算术运算的算术电路，以便对应于相应的存储器垫并且以级联形式电连接。 初始级算术电路的输入端被提供地址设定固定地址信号。 提供给下一个和后续运算电路的输入信号或从其输出的信号被定义为自己分配的地址信号（分配给相应的存储器垫的那些）。 与上述每个运算电路相关联地提供的比较器比较了存储器访问时输入的地址信号和地址信号之间的一致性。 基于所得到的一致信号来选择相应的存储器垫。

公开(公告)号：US6069834A

公开(公告)日：2000-05-30

申请号：US813900

申请日：1997-03-07

申请人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

发明人： Takao Watanabe ,  Kazushige Ayukawa ,  Ryo Fujita ,  Kazumasa Yanagisawa ,  Hitoshi Tanaka

IPC分类号： G06F17/50 ,  G11C7/00 ,  G11C7/02 ,  G11C7/10 ,  G11C8/12 ,  H01L27/108 ,  G11C8/00

CPC分类号： G11C7/02 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1042 ,  G11C7/1072 ,  H01L27/10897

摘要： A semiconductor IC device is designed using a memory core with a plurality of I/O lines, a transfer circuit module and a logic library which are produced beforehand and stored in a data base. The memory core and a logic circuit are arranged so that their I/O lines extend in the same direction. A transfer circuit including plural stages of switch groups is arranged between the I/O lines of the memory core and the I/O lines of the logic circuit. Switches forming each stage of switch group are formed between the I/O lines of the memory core and the I/O lines of the logic circuit. When one stage of or a small number of stages of switch groups are turned on, the I/O lines of the memory core and the I/O lines of the logic circuit are turned on, thereby forming a desired transfer pattern. The memory core is constructed by the combination of functional modules such as an amplifier module, a bank module and a power supply module. In the bank module are arranged row-system circuits which operate independently of each other and a multiplicity of I/O lines which extend in a bit line direction.

公开(公告)号：US5965909A

公开(公告)日：1999-10-12

申请号：US936744

申请日：1997-09-25

申请人： Hitoshi Tanaka

发明人： Hitoshi Tanaka

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L31/0328

CPC分类号： H01L29/7783

摘要： The semiconductor device comprises a substrate, a channel layer formed on the substrate, a first barrier layer formed on the channel layer, being an indirect transition semiconductor layer containing Al and P and being not lattice-matched with the substrate, and an electrode formed above the first barrier layer. The first barrier layer having a wide band gap and having a high barrier to electrons is formed below the electrodes, whereby a high gate turn-on voltage can be available.

摘要翻译： 半导体器件包括衬底，形成在衬底上的沟道层，形成在沟道层上的第一势垒层，是包含Al和P并且不与衬底晶格匹配的间接转移半导体层，以及上面形成的电极 第一阻隔层。 在电极下方形成具有宽带隙并具有高电子势垒的第一阻挡层，由此可以获得高栅极导通电压。

公开(公告)号：US5946689A

公开(公告)日：1999-08-31

申请号：US979946

申请日：1997-11-26

申请人： Hiroyuki Yanaka ,  Satoshi Wakayama ,  Takeo Maruyama ,  Hitoshi Tanaka ,  Norifumi Nishikawa ,  Hideyuki Takatani

发明人： Hiroyuki Yanaka ,  Satoshi Wakayama ,  Takeo Maruyama ,  Hitoshi Tanaka ,  Norifumi Nishikawa ,  Hideyuki Takatani

IPC分类号： G06F12/00 ,  G06F17/30

CPC分类号： G06F17/30575 ,  Y10S707/99953

摘要： In a distributed database system including a plurality of database systems each having a database, wherein a database possessed by one of the database systems serves as an original database, and databases of the remaining database systems are produced by replicating the original database, the presence or absence of update contention of the same data in two database systems is detected. When data susceptible to detection of update contention is updated, an update serial number is produced for the data. The update serial number includes a system identifier for identifying a database system in which the data is updated and an update frequency related to the number of times of updates. The update serial number is accumulatively stored in an update serial number history associated with the data each time the data is updated. When the updated data and the update serial number history associated therewith are transferred to a receiving database system, the contents of the update serial number history associated with the received data is compared with the contents of an update serial number history associated with data corresponding to the received data (target data) in a database of the receiving database system, and a contending state of the received data with the target data is determined based on the result of the comparison in the receiving database system.

摘要翻译： 在包括多个数据库系统的分布式数据库系统中，每个数据库系统都具有数据库，其中由数据库系统之一拥有的数据库用作原始数据库，并且通过复制原始数据库来生成剩余数据库系统的数据库，存在或 检测到在两个数据库系统中不存在相同数据的更新争用。 当更新容易受检测更新争用的数据更新时，会为数据生成更新序列号。 更新序列号包括用于识别其中更新数据的数据库系统的系统标识符和与更新次数相关的更新频率。 每次更新数据时，更新序列号累积存储在与数据相关联的更新序列号历史中。 当与其相关联的更新数据和更新序列号历史被传送到接收数据库系统时，与接收到的数据相关联的更新序列号历史的内容与与对应于数据的数据相关联的更新序列号历史的内容进行比较 在接收数据库系统的数据库中接收到的数据（目标数据），并且基于接收数据库系统中的比较结果来确定与目标数据的接收数据的竞争状态。

公开(公告)号：US5945683A

公开(公告)日：1999-08-31

申请号：US906389

申请日：1997-08-05

申请人： Tatsuro Ohkawa ,  Yoshihisa Ooae ,  Hitoshi Tanaka ,  Hiroshi Yasuda

发明人： Tatsuro Ohkawa ,  Yoshihisa Ooae ,  Hitoshi Tanaka ,  Hiroshi Yasuda

IPC分类号： H01J37/06 ,  H01J37/063 ,  H01J37/305 ,  H01L21/027

CPC分类号： H01J37/063 ,  H01J2237/30433 ,  H01J2237/3175

摘要： An electron beam exposure device includes an alignment optical system; an electromagnetic lens system; a stage on which the sample is provided; and an electron gun. The electron gun is comprised of an electron generating source; an electron generating source heating element which generates heat for increasing the temperature of the electron generating source; a supporting member which supports the electron generating source and the electron generating source heating element; and a Wehnelt. The electron beam exposure device is provided with at least one auxiliary heating element located at respective portion thermally connected to the electron generating source heating element.

摘要翻译： 电子束曝光装置包括对准光学系统; 电磁透镜系统; 提供样品的阶段; 和电子枪。 电子枪由电子发生源组成; 电子发生源加热元件，其产生用于增加电子发生源的温度的热量; 支撑电子发生源和电子发生源加热元件的支撑构件; 和一个Wehnelt。 电子束曝光装置设置有至少一个位于与电子发生源加热元件热连接的相应部分处的辅助加热元件。

公开(公告)号：US5940226A

公开(公告)日：1999-08-17

申请号：US924663

申请日：1997-09-05

申请人： Hitoshi Tanaka

发明人： Hitoshi Tanaka

IPC分类号： G02B7/10 ,  G02B7/02 ,  G02B21/00 ,  G02B27/00

CPC分类号： G02B7/10

摘要： A light intercepting mechanism of a zoom lens barrel includes a movable lens frame which holds a frontmost lens group, and a drive ring which is fitted on an outer peripheral surface of the movable lens frame to relatively rotate, so that when the relative rotation of the drive ring occurs, the movable lens frame is moved in the optical axis direction. The movable lens frame has a dual-cylinder structure having a closed front end and an open rear end. The drive ring has a dual-cylinder structure having a closed rear end and an open front end. The movable lens frame having the dual-cylinder structure and the drive ring having the dual-cylinder structure are fitted one inside the each other.

摘要翻译： 变焦透镜镜筒的遮光机构包括保持最前面的透镜组的可移动透镜框架和装配在可移动透镜框架的外周表面上以相对旋转的驱动环，使得当相对旋转 驱动环发生，可动镜头框架在光轴方向移动。 可移动透镜框架具有双缸结构，其具有封闭的前端和敞开的后端。 驱动环具有双缸结构，其具有封闭的后端和敞开的前端。 具有双缸结构的可移动透镜框架和具有双气缸结构的驱动环彼此嵌合。

公开(公告)号：US5910924A

公开(公告)日：1999-06-08

申请号：US917706

申请日：1997-08-26

申请人： Hitoshi Tanaka ,  Masakazu Aoki ,  Kiyoo Itoh

发明人： Hitoshi Tanaka ,  Masakazu Aoki ,  Kiyoo Itoh

IPC分类号： G11C11/419 ,  G05F1/56 ,  G11C5/14 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  H01L21/8242 ,  H01L27/108 ,  H03K5/02 ,  H03K19/00 ,  H03K19/0944 ,  G11C7/00

CPC分类号： G11C5/147

摘要： A push-pull type output circuit is used in the differential amplifier of a voltage converter circuit. The threshold voltage of the driving transistor is set lower than the voltages of the transistors of the other circuits to operate the differential amplifier at a voltage higher than the power supply voltage. By using the push-pull type output circuit, the amplitude increases and it is possible to raise the capacity of the driving transistor. Moreover, by setting the threshold voltage of the driving transistor of the buffering circuit lower than the threshold voltages of the transistors of the other circuits, it is possible to further raise the driving capacity. Increase of the sub-threshold current due to lowering of the threshold voltage can be prevented by operating the differential amplifier at a voltage higher than the power supply voltage.

摘要翻译： 在电压转换器电路的差分放大器中使用推挽式输出电路。 驱动晶体管的阈值电压被设定为低于其他电路的晶体管的电压，以在高于电源电压的电压下操作差分放大器。 通过使用推挽型输出电路，振幅增大，可以提高驱动晶体管的容量。 此外，通过将缓冲电路的驱动晶体管的阈值电压设定为低于其他电路的晶体管的阈值电压，可以进一步提高驱动能力。 通过在高于电源电压的电压下操作差分放大器，可以防止由于阈值电压降低引起的亚阈值电流的增加。

公开(公告)号：US5706474A

公开(公告)日：1998-01-06

申请号：US455155

申请日：1995-05-31

申请人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Takeshi Sakata ,  Hitoshi Tanaka ,  Katsumi Matsuno

发明人： Kan Takeuchi ,  Masashi Horiguchi ,  Masakazu Aoki ,  Takeshi Sakata ,  Hitoshi Tanaka ,  Katsumi Matsuno

IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F13/16 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

CPC分类号： G11C7/1072 ,  G06F13/1689 ,  Y02B60/1228

摘要： A memory system is provided which is capable of eliminating deterioration in a processing rate due to possible signal delays between an input/output circuit and memory blocks. Complication of design is also reduced, especially when the scale and chip area of the memory system increase. A memory chip includes a plurality of memory array blocks each including an address buffer and an address counter, and operates on the basis of a local clock cycle. A control circuit is synchronous with a clock of an external device, and synchronous data-transfer circuitry includes a buffer which modulates the transfer rate of serial data which arrives from a memory array block at a local clock cycle so as to be synchronous with the clock of the control circuit. External clock signal lines are not distributed to the memory array blocks.

摘要翻译： 提供了一种能够消除由于输入/输出电路和存储块之间的信号延迟引起的处理速率恶化的存储器系统。 设计的复杂性也降低了，特别是当存储器系统的规模和芯片面积增加时。 存储器芯片包括多个存储器阵列块，每个存储器阵列块包括地址缓冲器和地址计数器，并且基于本地时钟周期进行操作。 控制电路与外部设备的时钟同步，同步数据传输电路包括一个缓冲器，该缓冲器调制在本地时钟周期从存储器阵列块到达的串行数据的传输速率，以便与时钟同步 的控制电路。 外部时钟信号线不分配给存储器阵列块。

公开(公告)号：US5526313A

公开(公告)日：1996-06-11

申请号：US104508

申请日：1993-08-10

申请人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

发明人： Jun Etoh ,  Kiyoo Itoh ,  Yoshiki Kawajiri ,  Yoshinobu Nakagome ,  Eiji Kume ,  Hitoshi Tanaka

IPC分类号： G11C5/14 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/147

摘要： Disclosed is a one-chip ULSI which can carry out the fixed operation in a wide range of power supply voltage (1 V to 5.5 V). This one-chip ULSI is composed of a voltage converter circuit(s) which serves to a fixed internal voltage for a wide range of power supply voltage, an input/output buffer which can be adapted to several input/output levels, a dynamid RAM(s) which can operate at a power supply voltage of 2 V or less, etc. This one-chip ULSI can be applied to compact and portable electronic devices such as a lap-top type personal computer, an electronic pocket note book, a solid-state camera, etc.

公开(公告)号：US5402376A

公开(公告)日：1995-03-28

申请号：US103781

申请日：1993-08-10

申请人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

发明人： Masashi Horiguchi ,  Jun Etoh ,  Masakazu Aoki ,  Yoshinobu Nakagome ,  Hitoshi Tanaka ,  Kiyoo Itoh

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C29/83 ,  G11C29/832 ,  G11C5/14

摘要： In a semiconductor memory, switch circuits are provided so as to inhibit voltage and signal supplies to each of the normal memory blocks when so required. On the other hand, a ROM is provided on the chip so as to store the address of a defective memory block which consumes an excessively large stand-by current when the semiconductor memory is in the stand-by mode. The switch circuits are controlled by the output of the ROM so as to inhibit the voltage and signal supply to the defective memory block. Then, a spare memory block which is substituted for the defective normal memory block receives the voltage and signal supply.

摘要翻译： 在半导体存储器中，提供开关电路，以便当需要时，禁止向每个正常存储器块提供电压和信号。 另一方面，在半导体存储器处于待机模式时，在芯片上提供ROM以存储消耗过大待机电流的缺陷存储块的地址。 开关电路由ROM的输出控制，以便阻止向缺陷存储器块提供电压和信号。 然后，代替有缺陷的正常存储块的备用存储块接收电压和信号供应。