公开(公告)号：US6147009A

公开(公告)日：2000-11-14

申请号：US107567

申请日：1998-06-29

申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Laurent Claude Perraud

发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Laurent Claude Perraud

IPC分类号： C23C16/32 ,  H01L21/312 ,  H01L21/316 ,  H01L23/29 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L21/76832 ,  C23C16/325 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/291 ,  H01L23/296 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/5222 ,  H01L2924/0002 ,  Y10T428/30

摘要： A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.

公开(公告)号：US6030904A

公开(公告)日：2000-02-29

申请号：US916001

申请日：1997-08-21

申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/768 ,  H01L21/477

CPC分类号： H01L21/312 ,  H01L21/31058 ,  H01L21/76807

摘要： A method for treating a film of carbon-based dielectric material such as diamond-like carbon to remove volatiles is described. The method incorporates the steps of providing a non-oxidizing ambient and heating the film above 350.degree. C. Heating may be by rapid thermal annealing. The dielectric constant of the material may be lowered. A stabilized carbon-based material is provided with less than 0.5% thickness or weight change/hour at a selected temperature at or below 400.degree. C. The invention overcomes the problem of dimensional instability during the incorporation of the material in integrated circuit chips as an intra and inter level dielectric.

摘要翻译： 描述了一种用于处理诸如类金刚石碳的碳基电介质材料膜以除去挥发物的方法。 该方法包括提供非氧化环境并将膜加热到350℃以上的步骤。加热可以通过快速热退火。 材料的介电常数可能会降低。 在等于或低于400℃的选定温度下，稳定的碳基材料提供小于0.5％的厚度或重量变化/小时。本发明克服了在将材料掺入集成电路芯片中时的尺寸不稳定性的问题，作为 内部和中间电介质。

公开(公告)号：US5981000A

公开(公告)日：1999-11-09

申请号：US058651

申请日：1998-04-10

申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel

发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel

IPC分类号： C23C16/26 ,  C23C16/509 ,  C23C16/56 ,  H01L21/314 ,  B05D3/06

CPC分类号： C23C16/5096 ,  C23C16/26 ,  C23C16/56 ,  H01L21/3146 ,  Y10S427/103 ,  Y10S427/104

摘要： A method for fabricating a thermally stable carbon-based low dielectric constant film such as a hydrogenated amorphous carbon film or a diamond-like carbon film in a parallel plate chemical vapor deposition process utilizing plasma enhanced chemical vapor deposition process is disclosed. Electronic devices containing insulating layers of thermally stable carbon-based low dielectric constant materials that are prepared by the method are further disclosed. In order to render the carbon-based low dielectric constant film thermally stable, i.e., at a temperature of at least 400.degree. C., the films are heat treated at a temperature of not less than 350.degree. C. for at least 0.5 hour. To enable the fabrication of thermally stable carbon-based low dielectric constant film, specific precursor materials such as cyclic hydrocarbons should be used, for instance, cyclohexane or benzene. The geometry of the chemical vapor deposition chamber is important in making the present invention thermally stable low dielectric constant films in order to achieve a specific bias voltage on the substrate onto which the electronic structure is formed.

摘要翻译： 公开了一种利用等离子体增强化学气相沉积工艺在平行板化学气相沉积工艺中制造热稳定性碳基低介电常数膜的方法，例如氢化无定形碳膜或类金刚石碳膜。 还公开了通过该方法制备的含有热稳定性碳基低介电常数材料绝缘层的电子器件。 为了使碳基低介电常数膜热稳定，即在至少400℃的温度下，将膜在不低于350℃的温度下热处理至少0.5小时。 为了制造热稳定性的碳系低介电常数膜，可以使用环状烃等环状烃等特定的前体材料。 化学气相沉积室的几何形状对于使本发明热稳定的低介电常数膜是重要的，以便在其上形成电子结构的基板上实现特定的偏置电压。

公开(公告)号：US5884990A

公开(公告)日：1999-03-23

申请号：US949314

申请日：1997-10-14

申请人： Joachim Norbert Burghartz ,  Daniel Charles Edelstein ,  Christopher Vincent Jahnes ,  Cyprian Emeka Uzoh

发明人： Joachim Norbert Burghartz ,  Daniel Charles Edelstein ,  Christopher Vincent Jahnes ,  Cyprian Emeka Uzoh

IPC分类号： H01F17/00 ,  H01F17/06 ,  H01F27/28 ,  H01F30/16 ,  H01F41/04 ,  H01L23/522 ,  H01F5/00 ,  H01F7/06

CPC分类号： H01L23/5227 ,  H01F17/0006 ,  H01F17/0033 ,  H01F27/2804 ,  H01F27/2895 ,  H01F30/16 ,  H01F41/042 ,  H01F41/046 ,  H01F17/06 ,  H01L2924/0002 ,  Y10T29/4902

摘要： High quality factor (Q) spiral and toroidal inductor and transformer are disclosed that are compatible with silicon very large scale integration (VLSI) processing, consume a small IC area, and operate at high frequencies. The spiral inductor has a spiral metal coil deposited in a trench formed in a dielectric layer over a substrate. The metal coil is enclosed in ferromagnetic liner and cap layers, and is connected to an underpass contact through a metal filled via in the dielectric layer. The spiral inductor also includes ferromagnetic cores lines surrounded by the metal spiral coil. A spiral transformer is formed by vertically stacking two spiral inductors, or placing them side-by-side over a ferromagnetic bridge formed below the metal coils and cores lines. The toroidal inductor includes a toroidal metal coil with a core having ferromagnetic strips. The toroidal metal coil is segmented into two coils each having a pair of ports to form a toroidal transformer.

摘要翻译： 公开了与硅非常大规模集成（VLSI）处理兼容的高质量因子（Q）螺旋和环形电感器和变压器，消耗小的IC区域并在高频下操作。 螺旋电感器具有沉积在形成在衬底上的电介质层中的沟槽中的螺旋金属线圈。 金属线圈封装在铁磁衬垫和盖层中，并通过电介质层中的金属填充通孔连接到地下通道接触。 螺旋电感器还包括由金属螺旋线圈包围的铁磁芯线。 通过垂直堆叠两个螺旋电感器或将它们并排放置在形成在金属线圈和芯线下方的铁磁桥上，形成螺旋形变压器。 环形电感器包括具有铁磁条的芯的环形金属线圈。 环形金属线圈被分成两个线圈，每个线圈具有一对端口以形成环形变压器。

公开(公告)号：US20110109405A1

公开(公告)日：2011-05-12

申请号：US13007130

申请日：2011-01-14

申请人： Leena Paivikki Buchwalter ,  Kevin Kok Chan ,  Timothy Joseph Dalton ,  Christopher Vincent Jahnes ,  Jennifer Louise Lund ,  Kevin Shawn Petrarca ,  James Louis Speidell ,  James Francis Ziegler

发明人： Leena Paivikki Buchwalter ,  Kevin Kok Chan ,  Timothy Joseph Dalton ,  Christopher Vincent Jahnes ,  Jennifer Louise Lund ,  Kevin Shawn Petrarca ,  James Louis Speidell ,  James Francis Ziegler

IPC分类号： H03H9/24

CPC分类号： B81C1/00246 ,  B81B2201/0271 ,  B81C1/0023 ,  B81C2203/0735 ,  H03H3/0072 ,  H03H9/2405

摘要： A microelectromechanical system (MEMS) resonator or filter including a first conductive layer, one or more electrodes patterned in the first conductive layer which serve the function of signal input, signal output, or DC biasing, or some combination of these functions, an evacuated cavity, a resonating member comprised of a lower conductive layer and an upper structural layer, a first air gap between the resonating member and one or more of the electrodes, an upper membrane covering the cavity, and a second air gap between the resonating member and the upper membrane.

摘要翻译： 一种微机电系统（MEMS）谐振器或滤波器，其包括第一导电层，在第一导电层中图案化的一个或多个电极，其用于信号输入，信号输出或DC偏置的功能，或这些功能的某些组合;抽真空腔 ，由下导电层和上结构层构成的谐振构件，在谐振构件和一个或多个电极之间的第一气隙，覆盖空腔的上膜，以及谐振构件和第二气隙之间的第二气隙 上膜。

公开(公告)号：US20090091037A1

公开(公告)日：2009-04-09

申请号：US11866455

申请日：2007-10-03

申请人： Solomon Assefa ,  Gregory Costrini ,  Christopher Vincent Jahnes ,  Michael J. Rooks ,  Jonathan Zanhong Sun

发明人： Solomon Assefa ,  Gregory Costrini ,  Christopher Vincent Jahnes ,  Michael J. Rooks ,  Jonathan Zanhong Sun

IPC分类号： H01L21/768 ,  H01L23/52

CPC分类号： H01L43/12

摘要： A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.

摘要翻译： 在集成电路中形成由垂直接触件接触的柱结构。 硬掩模被形成并用于对柱结构的至少一部分进行图案化。 硬掩模包含碳。 随后，去除硬掩模。 然后将导电材料沉积在先前由硬掩模占据的区域中以形成垂直接触。 硬掩模可以例如包括类金刚石碳。 柱结构可以具有小于约100纳米的宽度或直径。

公开(公告)号：US07098476B2

公开(公告)日：2006-08-29

申请号：US10949837

申请日：2004-09-24

申请人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina E. Babich ,  Roy Arthur Carruthers ,  Timothy Joseph Dalton ,  Alfred Grill ,  Jeffrey Curtis Hedrick ,  Christopher Vincent Jahnes ,  Ebony Lynn Mays ,  Laurent Perraud ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L31/20 ,  H01L29/04

CPC分类号： H01L21/76831 ,  H01L21/7681 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A novel air-gap-containing interconnect wiring structure is described incorporating a solid low-k dielectric in the via levels, and a composite solid plus air-gap dielectric in the wiring levels. Also provided is a method for forming such an interconnect structure. The method is readily scalable to interconnect structures containing multiple wiring levels, and is compatible with Dual Damascene Back End of the Line (BEOL) processing.

公开(公告)号：US06724086B1

公开(公告)日：2004-04-20

申请号：US09603256

申请日：2000-06-23

申请人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Laurent Claude Perraud

发明人： Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Laurent Claude Perraud

IPC分类号： H01L2348

CPC分类号： H01L21/76832 ,  C23C16/325 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/291 ,  H01L23/296 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10T428/30 ,  H01L2924/00

摘要： A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.

摘要翻译： 公开了可用作IC芯片中的互连电介质的低介电常数，热稳定的氢化氧化硅碳膜。 还公开了利用等离子体增强化学气相沉积技术制造热稳定的氢化氧化硅碳低介电常数膜的方法。 还公开了通过该方法制备的包含热稳定的氢化氧化硅碳低介电常数材料的绝缘层的电子器件。 为了制造热稳定的氢化氧化硅碳低介电常数膜，优选具有环结构的特定的前体材料。

公开(公告)号：US06448655B1

公开(公告)日：2002-09-10

申请号：US09067439

申请日：1998-04-28

申请人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

发明人： Katherina Babich ,  Alessandro Callegari ,  Stephen Alan Cohen ,  Alfred Grill ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Sampath Purushothaman ,  Katherine Lynn Saenger

IPC分类号： H01L2348

CPC分类号： H01L21/76825 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31058 ,  H01L21/3127 ,  H01L21/31629 ,  H01L21/76814 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for providing regions of substantially lower fluorine content in a fluorine containing dielectric is described incorporating exposing a region to ultraviolet radiation and annealing at an elevated temperature to remove partially disrupted fluorine from the region. The invention overcomes the problem of fluorine from a fluorine containing dielectric reacting with other materials while maintaining a bulk dielectric material of sufficiently high or original fluorine content to maintain an effective low dielectric constant in semiconductor chip wiring interconnect structures.

摘要翻译： 描述了在含氟电介质中提供基本上较低氟含量的区域的方法，其包括将区域暴露于紫外线辐射并在升高的温度下退火以从该区域去除部分被破坏的氟。 本发明克服了与含氟介质与其他材料反应的氟的问题，同时保持足够高或原始氟含量的体电介质材料，以保持半导体芯片布线互连结构中有效的低介电常数。

公开(公告)号：US06448176B1

公开(公告)日：2002-09-10

申请号：US09699900

申请日：2000-10-30

申请人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

发明人： Alfred Grill ,  John Patrick Hummel ,  Christopher Vincent Jahnes ,  Vishnubhai Vitthalbhai Patel ,  Katherine Lynn Saenger

IPC分类号： H01L214763

CPC分类号： H01L21/76811 ,  H01L21/76813 ,  H01L2221/1063 ,  Y10S438/945

摘要： The present invention relates to lithographic methods for forming a dual relief pattern in a substrate, and the application of such methods to fabricating multilevel interconnect structures in semiconductor chips by a Dual Damascene process in which dual relief cavities formed in a dielectric are filled with conductive material to form the wiring and via levels. The invention comprises a twice patterned single mask layer Dual Damascene process modified by the addition of an easy-to-integrate sidewall liner to protect organic interlevel and intralevel dielectrics from potential damage induced by photoresist stripping steps during lithographic rework. The invention further comprises a method for forming a dual pattern hard mask which may be used to form dual relief cavities for use in Dual Damascene processing, said dual pattern hard mask comprising a first set of one or more layers with a first pattern, and a second set of one or more layers with a second pattern.

摘要翻译： 本发明涉及用于在衬底中形成双浮雕图案的平版印刷方法，以及通过双镶嵌工艺制造半导体芯片中的多层互连结构的方法，其中形成在电介质中的双浮雕空穴填充有导电材料 形成布线和通孔层。 本发明包括通过添加易于整合的侧壁衬里而修改的两次图案化单掩膜层双镶嵌工艺，以保护有机层间和层间电介质免受光刻胶剥离步骤在光刻返工期间引起的潜在损伤。 本发明还包括一种用于形成双重图案硬掩模的方法，该双面图案硬掩模可用于形成用于双镶嵌处理​​的双浮雕空腔，所述双图案硬掩模包括具有第一图案的一层或多层第一组和 具有第二图案的第二组一层或多层。