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40 条记录 (耗时 0.036 秒)

    Integrated Voltage Regulator with Embedded Passive Device(s)
    32.
    发明申请
    Integrated Voltage Regulator with Embedded Passive Device(s) 审中-公开
    带嵌入式无源器件的集成稳压器

    公开(公告)号：US20110050334A1

    公开(公告)日：2011-03-03

    申请号：US12552321

    申请日：2009-09-02

    申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    IPC分类号： H01L25/00

    CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

    摘要： A semiconductor packaging system has a packaging substrate into which inductors and/or capacitors are partially or completely embedded. An active portion of a voltage regulator is mounted on the packaging substrate and supplies regulated voltage to a die also mounted on the packaging substrate. Alternatively, the active portion of the voltage regulator is integrated into the die the voltage regulator supplies voltage to. The voltage regulator cooperates with the inductors and/or capacitors to supply voltage to the die. The inductors may be through vias in the packaging substrate. For additional inductance, through vias in a printed circuit board on which the packaging substrate is mounted may couple to the through vias in the packaging substrate.

    摘要翻译： 半导体封装系统具有其中部分或完全嵌入电感器和/或电容器的封装衬底。 电压调节器的有源部分安装在封装基板上，并将稳定的电压提供给也安装在封装基板上的管芯。 或者，电压调节器的有源部分集成到管芯中，电压调节器将电压提供给。 电压调节器与电感器和/或电容器配合以向模具提供电压。 电感器可以穿过封装衬底中的通孔。 对于额外的电感，通过安装封装衬底的印刷电路板中的通孔可以耦合到封装衬底中的通孔。

    Non-Volatile State Retention Latch
    33.
    发明申请
    Non-Volatile State Retention Latch 有权
    非易失性状态保持闭锁

    公开(公告)号：US20100141322A1

    公开(公告)日：2010-06-10

    申请号：US12328042

    申请日：2008-12-04

    申请人： Lew G. Chua-Eoan

    发明人： Lew G. Chua-Eoan

    IPC分类号： H03K3/037 ,  H03K3/289

    CPC分类号： G11C11/16 ,  G11C11/005 ,  G11C14/0081

    摘要： Electronic circuits use latches including a magnetic tunnel junction (MTJ) structure and logic circuitry arranged to produce a selective state in the MTJ structure. Because the selective state is maintained magnetically, the state of the latch or electronic circuit can be maintained even while power is removed from the electronic device.

    摘要翻译： 电子电路使用包括磁隧道结（MTJ）结构的锁存器和被布置成在MTJ结构中产生选择状态的逻辑电路。 由于选择状态是以磁性方式保持的，所以即使从电子设备移除电力，也可以保持闩锁或电子电路的状态。

    Gate Level Reconfigurable Magnetic Logic
    34.
    发明申请
    Gate Level Reconfigurable Magnetic Logic 有权
    门级可重构磁逻辑

    公开(公告)号：US20100039136A1

    公开(公告)日：2010-02-18

    申请号：US12192386

    申请日：2008-08-15

    申请人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

    发明人： Lew G. Chua-Eoan ,  Xiaochun Zhu ,  Zhi Zhu

    IPC分类号： H03K19/173

    CPC分类号： G11C11/16

    摘要： A re-programmable gate logic includes a plurality of non-volatile re-configurable resistance state-based memory circuits in parallel, wherein the circuits are re-configurable to implement or change a selected gate logic, and the plurality of non-volatile re-configurable resistance state-based memory circuits are each adapted to receive a logical input signal. An evaluation switch in series with the plurality of parallel non-volatile re-configurable resistance state-based memory circuits is configured to provide an output signal based on the programmed states of the memory circuits. A sensor is configured to receive the output signal and provide a logical output signal on the basis of the output signal and a reference signal provided to the sensor. The reconfigurable logic may be implemented based on using spin torque transfer (STT) magnetic tunnel junction (MTJ) magnetoresistance random access memory (MRAM) as the re-programmable memory elements. The logic configuration is retained without power.

    摘要翻译： 可再编程门逻辑并行包括多个非易失性可重新配置的基于电阻状态的存储器电路，其中电路可重新配置以实现或改变所选择的门逻辑， 可配置电阻状态的存储器电路各自适于接收逻辑输入信号。 与多个并行非易失性可重配置电阻状态存储电路串联的评估开关被配置为基于存储器电路的编程状态提供输出信号。 传感器被配置为接收输出信号并且基于输出信号和提供给传感器的参考信号来提供逻辑输出信号。 可重构逻辑可以基于使用自旋转矩传递（STT）磁性隧道结（MTJ）磁阻随机存取存储器（MRAM）作为可再编程存储器元件来实现。 逻辑配置在没有电源的情况下保留。

    Integrated voltage regulator method with embedded passive device(s)
    36.
    发明授权
    Integrated voltage regulator method with embedded passive device(s) 有权
    嵌入式无源器件的集成稳压器方法

    公开(公告)号：US08692368B2

    公开(公告)日：2014-04-08

    申请号：US13367932

    申请日：2012-02-07

    申请人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    发明人： Yuancheng Christopher Pan ,  Lew G. Chua-Eoan ,  Zhi Zhu ,  Junmou Zhang

    IPC分类号： H01L23/34

    CPC分类号： H01L25/16 ,  H01L23/642 ,  H01L23/645 ,  H01L25/0652 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H02M3/00 ,  H05K1/0262 ,  H05K1/141 ,  H05K1/185

    摘要： A stacked integrated circuit (IC) device includes a semiconductor IC having an active face, and an interconnect structure. The active face receives a regulated voltage from a voltage regulator (MEG). An active portion of the VREG, which supplies the regulated voltage to the semiconductor IC is coupled to the interconnect structure. A packaging substrate includes one or more inductors including a first set of through vias. The first set of through vias are coupled to the interconnect structure and cooperate with the active portion to provide the regulated voltage for the semiconductor IC. The IC also includes a printed circuit board (PCB) coupled to the packaging substrate. The PCB includes a second set of through vias coupled to the first set of through vias. The IC also includes one or more conducting paths on the PCB. The conducting path(s) couple together at least two through vias of the second set of through vias.

    摘要翻译： 堆叠集成电路（IC）装置包括具有有源面的半导体IC和互连结构。 主动面从电压调节器（MEG）接收稳压电压。 将调节电压提供给半导体IC的VREG的有效部分耦合到互连结构。 包装衬底包括一个或多个包括第一组通孔的电感器。 第一组通孔耦合到互连结构并与有源部分配合以提供用于半导体IC的调节电压。 IC还包括耦合到封装基板的印刷电路板（PCB）。 PCB包括耦合到第一组通孔的第二组通孔。 IC还包括PCB上的一个或多个导电路径。 导电路径将第二组通孔的至少两个通孔耦合在一起。

    Semiconductor Device Having On-Chip Voltage Regulator
    37.
    发明申请
    Semiconductor Device Having On-Chip Voltage Regulator 有权
    具有片上稳压器的半导体器件

    公开(公告)号：US20120218005A1

    公开(公告)日：2012-08-30

    申请号：US13034845

    申请日：2011-02-25

    申请人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

    发明人： Lew G. Chua-Eoan ,  Charles Matar ,  Matthew L. Severson ,  Xiaohua Kong

    IPC分类号： G05F1/10 ,  H03B21/00

    CPC分类号： G06F1/26 ,  G06F1/3296 ,  H03K19/0016 ,  Y02D10/172

    摘要： A semiconductor device having an on-chip voltage regulator to control on-chip voltage regulation and methods for on-chip voltage regulation are disclosed. A semiconductor device includes a circuit positioned between a ground bus and a power bus. A power switch array is positioned between the circuit and one of the ground bus or the power bus to generate a virtual voltage across the circuit. A monitor is positioned between the ground bus and the power bus. The monitor is configured to simulate a critical path of the circuit and to output a voltage adjust signal based on an output of the simulated critical path. A controller is configured to receive the voltage adjust signal and to output a control signal to the power switch array to control the virtual voltage.

    摘要翻译： 公开了一种具有用于控制片上电压调节的片上电压调节器和片上电压调节方法的半导体器件。 半导体器件包括位于接地总线和电源总线之间的电路。 电源开关阵列位于电路和其中一个接地总线或电源总线之间，以在电路两端产生虚拟电压。 监视器位于接地总线和电源总线之间。 监视器被配置为模拟电路的关键路径并且基于模拟关键路径的输出来输出电压调整信号。 控制器被配置为接收电压调整信号并将控制信号输出到电源开关阵列以控制虚拟电压。

    Leakage Reduction in Electronic Circuits
    39.
    发明申请
    Leakage Reduction in Electronic Circuits 有权
    电子线路漏电减少

    公开(公告)号：US20100321102A1

    公开(公告)日：2010-12-23

    申请号：US12486159

    申请日：2009-06-17

    申请人： Xiaohua Kong ,  Lew G. Chua-Eoan

    发明人： Xiaohua Kong ,  Lew G. Chua-Eoan

    IPC分类号： G05F1/10

    CPC分类号： H03K19/0013 ,  H03K19/0016

    摘要： In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

    摘要翻译： 在一个实施例中，用于减少电子电路（例如，CMOS电路）中的泄漏的装置包括被配置为选择性地将电压耦合到电子电路的逻辑部分的电源开关晶体管。 电力开关晶体管在电子电路的有效模式期间接收第一电压，并且在电子电路的睡眠模式期间接收第二电压。 功率开关晶体管具有在休眠模式期间使用第一电压偏置的体区。 功率开关晶体管具有在睡眠模式期间使用第一电压偏置的栅极区域。

    Method and apparatus for arithmetic operation on vectored data
    40.
    发明授权
    Method and apparatus for arithmetic operation on vectored data 失效
    矢量数据的算术运算方法和装置

    公开(公告)号：US06574651B1

    公开(公告)日：2003-06-03

    申请号：US09411620

    申请日：1999-10-01

    申请人： Jeffrey Cui ,  Stephane Rossignol ,  Lew G. Chua-Eoan

    发明人： Jeffrey Cui ,  Stephane Rossignol ,  Lew G. Chua-Eoan

    IPC分类号： G06F738

    CPC分类号： G06F7/5324 ,  G06F7/4991 ,  G06F7/49921

    摘要： A method of multiplying 32-bit values includes decomposing each multiplicand into its 16-bit components. This approach leads to a processor core design which permits re-use of much of the logic in the multiplication unit. The multiplication unit includes a selector which can feed various-sized data formats to the same multiplier circuits. Multiple data transformation paths are provided and feed into a single compression circuit and a single configurable full adder circuit.

    摘要翻译： 32位值相乘的方法包括将每个被乘数分解成其16位分量。 这种方法导致处理器核心设计，允许重新使用乘法单元中的大部分逻辑。 乘法单元包括可以将各种尺寸的数据格式馈送到相同的乘法器电路的选择器。 提供多个数据转换路径并馈入单个压缩电路和单个可配置全加器电路。