公开(公告)号：US20070115018A1

公开(公告)日：2007-05-24

申请号：US11163948

申请日：2005-11-04

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence Clevenger ,  Andrew Cowley ,  Ronald Filippi ,  Jason Gill ,  Tom Lee ,  Baozhen Li ,  Paul McLaughlin ,  Du Nguyen ,  Hazara Rathore ,  Timothy Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).

摘要翻译： 提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。 至少一些导电互连件包括金属板，金属连接线和上金属通孔。 所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。 金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。 上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

公开(公告)号：US20070267386A1

公开(公告)日：2007-11-22

申请号：US11833283

申请日：2007-08-03

申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01B13/00 ,  B44C1/22

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US08563419B2

公开(公告)日：2013-10-22

申请号：US13418659

申请日：2012-03-13

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel C. Edelstein

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Daniel C. Edelstein

IPC分类号： H01L21/4763

CPC分类号： H01L23/5329 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing the IC is provided, and more particularly, a method of fabricating a cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage. The method includes forming an interconnect in an insulation material, and selectively depositing a metal cap material on the interconnect. The metal cap material includes RuX, where X is at least one of Boron and Phosphorous.

摘要翻译： 提供了一种制造IC的方法，更具体地说，涉及一种基本上消除电迁移（EM）损伤的制造用于后端（BEOL）互连的帽的方法。 该方法包括在绝缘材料中形成互连，并且在互连上选择性地沉积金属帽材料。 金属帽材料包括RuX，其中X是硼和磷中的至少一种。

公开(公告)号：US08535991B2

公开(公告)日：2013-09-17

申请号：US12688254

申请日：2010-01-15

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： H01L21/82

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

公开(公告)号：US08120179B2

公开(公告)日：2012-02-21

申请号：US12615354

申请日：2009-11-10

申请人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

发明人： Kaushik Chanda ,  Cathryn J. Christiansen ,  Daniel C. Edelstein ,  Satyanarayana V. Nitta ,  Son V. Nguyen ,  Shom Ponoth ,  Hosadurga Shobha

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76849 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal interconnect structure includes at least a pair of metal lines, a cavity therebetween, and a dielectric metal-diffusion barrier layer located on at least one portion of walls of the cavity. After formation of a cavity between the pair of metal lines, the dielectric metal-diffusion barrier layer is formed on the exposed surfaces of the cavity. A dielectric material layer is formed above the pair of metal lines to encapsulate the cavity. The dielectric metal-diffusion barrier layer prevents diffusion of metal and impurities from one metal line to another metal line and vice versa, thereby preventing electrical shorts between the pair of metal lines.

摘要翻译： 金属互连结构包括至少一对金属线，它们之间的腔，以及位于腔的至少一部分壁上的介电金属扩散阻挡层。 在一对金属线之间形成空腔之后，在空腔的暴露表面上形成介电金属扩散阻挡层。 在一对金属线之上形成介电材料层以封装空腔。 电介质金属扩散阻挡层防止金属和杂质从一个金属线扩散到另一个金属线，反之亦然，从而防止一对金属线之间的电短路。

公开(公告)号：US07563704B2

公开(公告)日：2009-07-21

申请号：US11162666

申请日：2005-09-19

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence A. Clevenger ,  Yun-Yu Wang ,  Daewon Yang

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence A. Clevenger ,  Yun-Yu Wang ,  Daewon Yang

IPC分类号： H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.

摘要翻译： 提供了互连结构及其制造方法。 互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。 电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

公开(公告)号：US07479869B2

公开(公告)日：2009-01-20

申请号：US11869218

申请日：2007-10-09

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Chen

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Shyng-Tsong Chen

IPC分类号： H01C1/012

CPC分类号： H01L29/86 ,  H01L23/5228 ,  H01L2924/0002 ,  H04W36/08 ,  H04W88/08 ,  H04W88/18 ,  H01L2924/00

摘要： A metal resistor and resistor material are disclosed. The metal resistor may include an infused metal selected from the group consisting of: copper (Cu) infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W). The resistor material may include one of: copper (Cu) infused with at least one of silicon (Si), nitrogen (2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W), and aluminum infused with at least one of silicon (Si), nitrogen (N2), carbon (C), tantalum (Ta), titanium (Ti) and tungsten (W).

摘要翻译： 公开了一种金属电阻器和电阻器材料。 金属电阻器可以包括从由以下组成的组中输入的输入金属：铜（Cu），其输入硅（Si），氮（N 2），碳（C），钽（Ta），钛（Ti）和 钨（W）和铝（Si），氮（N 2），碳（C），钽（Ta），钛（Ti）和钨（W））中的至少一种的铝。 电阻材料可以包括以下之一：用硅（Si），氮（2），碳（C），钽（Ta），钛（Ti）和钨（W）中的至少一种注入的铜（Cu） 注入硅（Si），氮（N2），碳（C），钽（Ta），钛（Ti）和钨（W））中的至少一种。

公开(公告)号：US20090006014A1

公开(公告)日：2009-01-01

申请号：US11769265

申请日：2007-06-27

申请人： Kaushik Chanda ,  Fen Chen ,  Paul S. McLaughlin ,  Ernest Y. Wu

发明人： Kaushik Chanda ,  Fen Chen ,  Paul S. McLaughlin ,  Ernest Y. Wu

IPC分类号： G01R27/26 ,  G01B21/28

CPC分类号： H01L22/34 ,  H01L22/12

摘要： A method for determining a line-to-line spacing of a device. The method includes experimentally determining a slope kCA, experimentally determining a slope kSE and determining a line-to-line spacing of a device from the slope kCA and the slope kSE. A structure for performing the method includes a non-destructive line-to-line spacing characterization macro.

摘要翻译： 一种用于确定设备的行间距的方法。 该方法包括实验地确定斜率kCA，通过实验确定斜率kSE并且从斜率kCA和斜率kSE确定装置的线间距离。 用于执行该方法的结构包括非破坏性的线间距表征宏。

公开(公告)号：US20080231312A1

公开(公告)日：2008-09-25

申请号：US12154304

申请日：2008-05-22

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

摘要翻译： 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

公开(公告)号：US20060098862A1

公开(公告)日：2006-05-11

申请号：US10904434

申请日：2004-11-10

申请人： James Demarest ,  Kaushik Chanda ,  Derren Dunn ,  Yun-Yu Wang

发明人： James Demarest ,  Kaushik Chanda ,  Derren Dunn ,  Yun-Yu Wang

IPC分类号： G06K9/00

CPC分类号： G01N21/9501

摘要： Fail sites in a semiconductor are isolated through a difference image of a fail area and a healthy area. The fail area comprises an image of a semiconductor with a fail. The healthy area comprises an image of a semiconductor absent the fail or, in other words, an image of a semiconductor with healthy structure. Instructions cause a variation in the intensities of the difference image to appear at the fail site.

摘要翻译： 通过故障区域和健康区域的差异图像隔离半导体中的故障点。 故障区域包括具有故障的半导体的图像。 健康区域包括没有失败的半导体图像，换句话说，包括具有健康结构的半导体的图像。 说明会导致差异图像强度的变化出现在故障现场。