公开(公告)号：US07170167B2

公开(公告)日：2007-01-30

申请号：US10711536

申请日：2004-09-24

申请人： Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

发明人： Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

IPC分类号： H01L23/48

CPC分类号： H01L24/97 ,  H01L23/15 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29075 ,  H01L2224/83851 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

摘要翻译： 本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。 在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。 晶片通过其上的凸块或焊盘与玻璃基板连接。 在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。 之后，进行分割步骤，并获得多个芯片级封装结构。

公开(公告)号：US07071575B2

公开(公告)日：2006-07-04

申请号：US10904431

申请日：2004-11-10

申请人： Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

发明人： Bing-Chang Wu ,  Kun-Chih Wang ,  Mei-Ling Chao ,  Shiao-Shien Chen

IPC分类号： H01L23/12 ,  H00L23/48 ,  H00L29/40

CPC分类号： H01L24/05 ,  H01L23/53228 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05624 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00014

摘要： A semiconductor chip capable of implementing wire bonding over active circuits (BOAC) is provided. The semiconductor chip includes a bonding pad structure which includes a bondable metal pad, a top interconnection metal layer, a stress-buffering dielectric, and at least a first via plug between the bondable metal pad and the top interconnection metal layer. The semiconductor chip also includes at least an interconnection metal layer, at least a second via plug between the interconnection metal layer and the bonding pad structure, and an active circuit situated underneath the bonding pad structure on a semiconductor bottom.

摘要翻译： 提供了能够通过有源电路（BOAC）实现引线键合的半导体芯片。 该半导体芯片包括一个焊盘结构，该焊盘结构包括一个可粘合的金属焊盘，一个顶部互连金属层，一个应力缓冲电介质，以及至少一个可焊接的金属焊盘和顶部互连金属层之间的第一通孔塞。 半导体芯片还包括至少互连金属层，互连金属层和焊盘结构之间的至少第二通孔插头以及位于半导体底部上的焊盘结构下方的有源电路。

公开(公告)号：US20060073676A1

公开(公告)日：2006-04-06

申请号：US10950909

申请日：2004-09-27

申请人： Kuo-Ming Chen ,  Kun-Chih Wang ,  Hermen Liu ,  Paul Chen ,  Kai-Kuang Ho

发明人： Kuo-Ming Chen ,  Kun-Chih Wang ,  Hermen Liu ,  Paul Chen ,  Kai-Kuang Ho

IPC分类号： H01L21/78

CPC分类号： H01L21/78

摘要： A pre-process before cutting a wafer is described. The wafer comprises a plurality of scribe lines and a plurality of dies defined by the scribe lines, and a material layer covers the wafer. A pre-processing step is performed to remove the material layer on the scribe lines close to the corner regions of the dies. Removing the material layer at the corner regions before cutting the wafer is able to preserve the integrity of the corner regions of the cut dies.

摘要翻译： 描述切割晶片之前的预处理。 晶片包括多个划痕线和由划线限定的多个管芯，并且材料层覆盖晶片。 执行预处理步骤以去除靠近模具的拐角区域的划线上的材料层。 在切割晶片之前在拐角区域去除材料层能够保持切割模具的拐角区域的完整性。

公开(公告)号：US20060073232A1

公开(公告)日：2006-04-06

申请号：US10905802

申请日：2005-01-21

申请人： Kun-Chih Wang

发明人： Kun-Chih Wang

IPC分类号： B29D11/00

CPC分类号： B29C43/021 ,  B29C33/303 ,  B29C43/36 ,  B29C2043/3618 ,  B29D11/00413 ,  B29L2011/0016 ,  C03B11/08 ,  C03B2215/03 ,  C03B2215/60 ,  C03B2215/65 ,  C03B2215/72 ,  Y10S425/808 ,  Y10S425/812

摘要： An optical lens molding apparatus includes a cylindrical mold, a first mold core, a second mold core and a correctional ring. The first and the second mold core have a columnar shape and are disposed inside the cylindrical mold to form a cavity. Furthermore, the first and the second mold core have a planar portion at the end surface facing the cavity. The correctional ring is disposed on the planar portion of the second mold core. The correction ring corrects any face tilting of the molded optical lens due to the tilting of the first mold core. The present invention also provides a precision molding apparatus for forming precision parts.

摘要翻译： 光学透镜成型装置包括圆柱形模具，第一模芯，第二模芯和校正环。 第一和第二模芯具有圆柱形状并且设置在圆柱形模具内以形成空腔。 此外，第一和第二模芯在端面处具有面向空腔的平面部分。 校正环设置在第二模芯的平面部分上。 由于第一模芯的倾斜，校正环校正模制的光学透镜的任何表面倾斜。 本发明还提供一种用于形成精密部件的精密成形装置。

公开(公告)号：US20060048544A1

公开(公告)日：2006-03-09

申请号：US11151877

申请日：2005-06-13

申请人： Kun-Chih Wang

发明人： Kun-Chih Wang

IPC分类号： C03B11/08

CPC分类号： C23C16/30 ,  C03B11/086 ,  C03B2215/12 ,  C03B2215/24 ,  C03B2215/31 ,  C03B2215/34 ,  C23C16/0272

摘要： A molding core includes: a core body having an article-shaping surface; and a hard coating formed on the article-shaping surface of the core body and including a diamond-like carbon film that includes carbon, oxygen, and at least one bonding-enhancing element which is selected from silicon, titanium, aluminum, tungsten, tantalum, chromium, zirconium, vanadium, niobium, hafnium, and boron, and which forms covalence bonding with the carbon and the oxygen.

摘要翻译： 成形芯包括：具有制品成形表面的芯体; 以及形成在芯体的制品成形表面上的硬涂层，并且包括包含碳，氧和至少一种选自硅，钛，铝，钨，钽的粘合增强元素的类金刚石碳膜 ，铬，锆，钒，铌，铪和硼，并且与碳和氧键合形成共价。

公开(公告)号：US20050150253A1

公开(公告)日：2005-07-14

申请号：US11011130

申请日：2004-12-15

申请人： Kun-Chih Wang

发明人： Kun-Chih Wang

IPC分类号： C03B11/08 ,  C03B27/02 ,  C03B35/00 ,  C03C17/00

CPC分类号： C03C17/001 ,  C03B11/086 ,  C03B27/02 ,  C03C2218/15 ,  Y02P40/57

摘要： A method for making high precision hard film coating on a mold core comprises the following steps of: (a) providing a mold jig (200, 300) and a mold core (208, 308); (b) defining a through hole (206, 364) of a first inner diameter in the mold jig; (c) forming a rim (254, 354) of a second inner diameter on the inner side of the through hole, the second inner diameter being smaller than the first inner diameter; (d) configuring the mold core into a mold core including a body (212, 312) of a first external diameter and a top portion (250, 350) of a second external diameter, the second external diameter being smaller than the first external diameter to define a shoulder (252, 352) between the body and the top portion, the first external diameter being substantially equal to the first inner diameter and larger than the second inner diameter, the second external diameter being substantially equal to or smaller than the second inner diameter; and (e) coreing the mold core into the through hole of the mold jig from the bottom, the shoulder of the mold core engaging with the rim, the upper surface of the top portion of the mold core being substantially flush with the upper surface of the mold jig, and a groove (256, 356) being defined between the inner side of the through hole and the outer side of the top portion of the mold core. A device for performing this method is also disclosed.

摘要翻译： 在模芯上制造高精度硬膜的方法包括以下步骤：（a）提供模具夹具（200,300）和模芯（208,308）; （b）在所述模具夹具中限定第一内径的通孔（206,364）; （c）在所述通孔的内侧上形成第二内径的边缘（254,354），所述第二内径小于所述第一内径; （d）将模芯配置成包括第一外径的主体（212,312）和第二外径的顶部（250,350）的模芯，所述第二外径小于所述第一外径 以限定主体和顶部之间的肩部（252,352），第一外径基本上等于第一内径并且大于第二内径，第二外径基本上等于或小于第二内径 内径; 和（e）将模芯从底部夹入模具夹具的通孔中，模芯的凸缘与边缘接合，模芯顶部的上表面基本上与 模具夹具和在通孔的内侧和模芯的顶部的外侧之间限定的凹槽（256,356）。 还公开了一种用于执行该方法的装置。

公开(公告)号：US06707129B2

公开(公告)日：2004-03-16

申请号：US10020311

申请日：2001-12-18

申请人： Kun-Chih Wang

发明人： Kun-Chih Wang

IPC分类号： H01L2900

CPC分类号： H01L23/5329 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for using fuse structure integrated wire bonding on the substrate, and relates to methods for making the same are disclosed, in which an Al-fuse has an extra-etching process pattern by fuse-open mask and has been thinned down from Al-fuse thickness. The Al fuse structure integrated Al wire-bonding pad has two kind of thickness under fuse-open and for the other area. This invention makes the fuse easy to blow without suffering any bondability from wire bonding for packaging.

摘要翻译： 公开了一种用于在基板上使用熔丝结构集成引线接合的结构，并且涉及其制造方法，其中Al熔丝具有通过熔断器开口掩模的额外蚀刻工艺图案，并且已经从Al- 保险丝厚度。 Al熔丝结构集成铝线焊盘在熔断器开放和其他区域具有两种厚度。 本发明使得熔断器容易吹塑，而不会因包装引线接合而受到任何粘结。

公开(公告)号：US06371045B1

公开(公告)日：2002-04-16

申请号：US09360627

申请日：1999-07-26

申请人： Kun-Chih Wang ,  Chao-Ching Hsieh

发明人： Kun-Chih Wang ,  Chao-Ching Hsieh

IPC分类号： C23C1600

CPC分类号： H01J37/3266 ,  C23C14/046 ,  C23C14/165 ,  C23C14/351 ,  C23C14/358 ,  H01J37/34

摘要： The present invention provides a physical vapor deposition device for forming a metallic layer with a predetermined thickness on a semiconductor wafer. The PVD device comprises a chamber, a wafer chuck installed at the bottom end of the chamber through which the semiconductor wafer is hold horizontally, a metallic ion generator for generating metallic ions, an electric field generator for forming a vertical electric field above the wafer chuck that guides the metallic ions toward the wafer chuck, and a magnetic field generator. The magnetic field generator generates a magnetic field perpendicular to the direction of movement of the metallic ions to create a horizontal moving force on the metallic ions thus causing the metallic ions to deposit on the semiconductor wafer at a slant angle.

摘要翻译： 本发明提供一种用于在半导体晶片上形成具有预定厚度的金属层的物理气相沉积装置。 PVD装置包括一个室，安装在室底部的晶片卡盘，半导体晶片通过该底座水平保持，用于产生金属离子的金属离子发生器，用于在晶片卡盘上方形成垂直电场的电场发生器 其将金属离子引向晶片卡盘，以及磁场发生器。 磁场发生器产生垂直于金属离子移动方向的磁场，以在金属离子上产生水平移动力，从而使金属离子以倾斜角沉积在半导体晶片上。

公开(公告)号：US6013579A

公开(公告)日：2000-01-11

申请号：US176385

申请日：1998-10-21

申请人： Kun-Chih Wang ,  Tri-Rung Yew

发明人： Kun-Chih Wang ,  Tri-Rung Yew

IPC分类号： H01L21/768 ,  H01L21/00

CPC分类号： H01L21/76829 ,  H01L21/76802 ,  H01L21/76897

摘要： A self-aligned via process to prevent the via poisoning includes forming a hydrogen silsesquioxane layer on the substrate and over a pre-formed metal layer, forming an etching stop layer on the hydrogen silsesquioxane layer, forming an oxide layer on the etching stop layer, and then proceeding with a two-step etching process to form a via. The two-step etching process first patterns the oxide layer using a patterned photoresist layer as a mask, and then patterns the etching stop layer together with the hydrogen silsesquioxane layer using the patterned oxide layer as a mask. Because the etching stop layer prevents the hydrogen silsesquioxane layer from reacting with the oxygen plasma during the photoresist layer removal process, via poisoning is eliminated.

摘要翻译： 用于防止通路中毒的自对准通孔工艺包括在基板上和预成型的金属层上形成氢倍半硅氧烷层，在氢倍半硅氧烷层上形成蚀刻停止层，在蚀刻停止层上形成氧化物层， 然后进行两步蚀刻工艺以形成通孔。 两步蚀刻工艺首先使用图案化的光致抗蚀剂层作为掩模对氧化物层进行图案化，然后使用图案化氧化物层作为掩模，将蚀刻停止层与氢倍半硅氧烷层一起图案化。 因为蚀刻停止层防止在光致抗蚀剂层去除过程中氢倍半硅氧烷层与氧等离子体反应，消除了中毒。

公开(公告)号：US5976984A

公开(公告)日：1999-11-02

申请号：US1416

申请日：1997-12-30

申请人： Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

发明人： Coming Chen ,  Chih-Chien Liu ,  Kun-Chih Wang ,  Tri-Rung Yew

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/02

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76829 ,  H01L2924/0002

摘要： A method of making vias in a semiconductor IC device having adequate contact to the surface of the interconnects and without inadequate landing is disclosed. The method has interconnects formed in a metal layer on the substrate of the IC device, and a first dielectric layer is formed covering the surface of the interconnects. An etch-stopping layer is then formed on top of the first dielectric layer, followed by the formation of a second dielectric layer on top of the etch-stopping layer. A photoresist layer then covers the second dielectric layer and reveals the surface regions of the second dielectric layer designated for the formation of the vias. A main etching procedure is then performed to etch into the second dielectric layer down to the surface of the etch-stopping layer, thereby forming the first section of the vias. An over-etching procedure is then implemented to strip off the etch-stopping layer and further etches into the first dielectric layer and the etching is then stopped when the surface of the interconnects are revealed to conclude the formation of the vias.

摘要翻译： 公开了一种在半导体IC器件中形成通孔的方法，该半导体IC器件具有与互连表面的充分接触并且没有不足够的着陆。 该方法具有形成在IC器件的衬底上的金属层中的互连，并且覆盖互连表面的第一介电层被形成。 然后在第一介电层的顶部上形成蚀刻停止层，随后在蚀刻停止层的顶部形成第二电介质层。 光致抗蚀剂层然后覆盖第二电介质层并且显露指定用于形成通孔的第二电介质层的表面区域。 然后执行主蚀刻程序以蚀刻到第二介电层中，直到蚀刻停止层的表面，从而形成通孔的第一部分。 然后实施过蚀刻程序以剥离蚀刻停止层并进一步蚀刻到第一介电层中，然后当显露互连表面以终止形成通孔时，停止蚀刻。