公开(公告)号：US06828237B1

公开(公告)日：2004-12-07

申请号：US10662069

申请日：2003-09-11

申请人： Bor-Wen Chan ,  Fang-Cheng Chen ,  Hsien-Kuang Chiu ,  Yuan-Hung Chiu ,  Han-Jan Tao

发明人： Bor-Wen Chan ,  Fang-Cheng Chen ,  Hsien-Kuang Chiu ,  Yuan-Hung Chiu ,  Han-Jan Tao

IPC分类号： H01L21311

CPC分类号： H01L21/0338 ,  H01L21/28123 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823437

摘要： A plasma etch method for forming a patterned target layer within a microelectrcnic product forms an etch residue layer adjoining a patterned mask layer formed upon a blanket target layer. After removing the patterned mask layer, the etch residue layer is laterally increased to form a laterally increased etch residue layer. The laterally increased etch residue layer is employed as an etch mask for forming the patterned target layer from the blanket target layer. The method is particularly useful for forming gate electrodes within semiconductor products.

摘要翻译： 用于在微电子产品内形成图案化目标层的等离子体蚀刻方法形成邻接形成在覆盖目标层上的图案化掩模层的蚀刻残余层。 在去除图案化的掩模层之后，蚀刻残余层被横向增加以形成横向增加的蚀刻残留层。 使用横向增加的蚀刻残留层作为用于从覆盖目标层形成图案化目标层的蚀刻掩模。 该方法对于在半导体产品中形成栅电极特别有用。

公开(公告)号：US20050032386A1

公开(公告)日：2005-02-10

申请号：US10634001

申请日：2003-08-04

申请人： Ming-Ching Chang ,  Li-Te Lin ,  Yu-I Wang ,  Yuan-Hung Chiu ,  Hui-Jan Tao

发明人： Ming-Ching Chang ,  Li-Te Lin ,  Yu-I Wang ,  Yuan-Hung Chiu ,  Hui-Jan Tao

IPC分类号： H01L21/302 ,  H01L21/3213 ,  H01L21/461 ,  H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/32137

摘要： A method for improving a polysilicon gate electrode profile to avoid preferential RIE etching in a polysilicon gate electrode etching process including carrying out a multi-step etching process wherein at least one of a lower RF source power and RF bias power are reduced to complete a polysilicon etching process and an in-situ plasma treatment with an inert gas plasma is carried out prior to neutralize an electrical charge imbalance prior to carrying out an overetch step.

摘要翻译： 一种用于改善多晶硅栅极电极轮廓的方法，以避免在多晶硅栅极电极蚀刻工艺中的优先RIE蚀刻，包括进行多步蚀刻工艺，其中降低RF源功率和RF偏置功率中的至少一个以完成多晶硅 蚀刻工艺和惰性气体等离子体的原位等离子体处理在进行过蚀刻步骤之前中和电荷不平衡之前进行。

公开(公告)号：US08236659B2

公开(公告)日：2012-08-07

申请号：US12816519

申请日：2010-06-16

申请人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

发明人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US07678655B2

公开(公告)日：2010-03-16

申请号：US11495348

申请日：2006-07-28

申请人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

发明人： Hung Der Su ,  Ju-Wang Hsu ,  Yi-Chun Huang ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu ,  Jyh-Huei Chen ,  Jhon Jhy Liaw

IPC分类号： H01L21/336

CPC分类号： H01L29/6656 ,  H01L29/665 ,  H01L29/6653

摘要： A method for forming a field effect transistor device employs a conformal spacer layer formed upon a gate electrode. The gate electrode is employed as a mask for forming a lightly doped extension region within the semiconductor substrate and the gate electrode and conformal spacer layer are employed as a mask for forming a source/drain region within the semiconductor substrate. An anisotropically etched shaped spacer material layer is formed upon the conformal spacer layer and isotropically etched to enhance exposure of the source/drain region prior to forming a silicide layer thereupon.

摘要翻译： 用于形成场效应晶体管器件的方法使用形成在栅电极上的共形间隔层。 栅电极用作在半导体衬底内形成轻掺杂延伸区的掩模，并且栅电极和共形间隔层用作在半导体衬底内形成源极/漏极区的掩模。 在保形间隔层上形成各向异性蚀刻形状的间隔物层，并进行各向同性蚀刻，以在形成硅化物层之前增强源/漏区的曝光。

公开(公告)号：US07012027B2

公开(公告)日：2006-03-14

申请号：US10766596

申请日：2004-01-27

申请人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

发明人： Baw-Ching Perng ,  Yuan-Hung Chiu ,  Mei-Hui Sung ,  Peng-Fu Hsu

IPC分类号： H01L21/31

CPC分类号： H01L21/3065 ,  H01L21/28194 ,  H01L21/31122 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66583

摘要： A method is described for selectively etching a high k dielectric layer that is preferably a hafnium or zirconium oxide, silicate, nitride, or oxynitride with a selectivity of greater than 2:1 relative to silicon oxide, polysilicon, or silicon. The plasma etch chemistry is comprised of one or more halogen containing gases such as CF4, CHF3, CH2F2, CH3F, C4F8, C4F6, C5F6, BCl3, Br2, HF, HCl, HBr, HI, and NF3 and leaves no etch residues. An inert gas or an inert gas and oxidant gas may be added to the halogen containing gas. In one embodiment, a high k gate dielectric layer is removed on portions of an active area in a MOS transistor. Alternatively, the high k dielectric layer is used in a capacitor between two conducting layers and is selectively removed from portions of an ILD layer.

摘要翻译： 描述了一种相对于氧化硅，多晶硅或硅选择性地蚀刻优选为铪或氧化锆，硅酸盐，氮化物或氮氧化物的高k电介质层的方法，其选择性大于2:1。 等离子体蚀刻化学性质由一种或多种含卤素气体组成，例如CF 4，CH 3 3，CH 2 F 2， CH 3，CH 3，CH 3，CH 3，CH 3，CH 3，CH 3， C 5，C 5，F 5，BCl 3，Br 2，HF，HCl，HBr，HI， 和NF 3，并且不留下蚀刻残留物。 可以向含卤素的气体中加入惰性气体或惰性气体和氧化剂气体。 在一个实施例中，在MOS晶体管的有源区域的部分上去除高k栅极电介质层。 或者，高k电介质层用于两个导电层之间的电容器中，并且从ILD层的部分选择性地去除。

公开(公告)号：US06828198B2

公开(公告)日：2004-12-07

申请号：US10392120

申请日：2003-03-19

申请人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

发明人： Hung-Der Su ,  Shien-Yang Wu ,  Yung-Shun Chen ,  Tung-Heng Shie ,  Yuan-Hung Chiu

IPC分类号： H01L21336

CPC分类号： H01L21/823456 ,  H01L21/28123 ,  H01L21/32139

摘要： A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.

公开(公告)号：US06818553B1

公开(公告)日：2004-11-16

申请号：US10146315

申请日：2002-05-15

申请人： Mo-Chiun Yu ,  Yuan-Hung Chiu

发明人： Mo-Chiun Yu ,  Yuan-Hung Chiu

IPC分类号： H01L2144

CPC分类号： H01L21/31122 ,  H01L21/0276 ,  H01L21/31144 ,  H01L29/517

摘要： A method for forming a gate electrode comprising the following steps. A substrate having a high-k gate dielectric layer formed thereover is provided. A gate layer is formed over the high-k gate dielectric layer. A gate ARC layer is formed over the gate layer. The gate ARC layer and the gate layer are patterned to form a pattern gate ARC layer and a patterned gate layer. The high-k gate dielectric layer not under the patterned gate layer is partially etched and a smooth exposed upper surface of the patterned gate layer is formed. The partially etched high-k gate dielectric layer portions not under the patterned gate layer are removed to form the gate electrode comprised of the patterned gate layer and the etched high-k gate dielectric layer.

摘要翻译： 一种形成栅电极的方法，包括以下步骤。 提供了具有形成在其上的高k栅极电介质层的衬底。 在高k栅极电介质层上形成栅极层。 在栅极层上形成栅极ARC层。 栅极ARC层和栅极层被图案化以形成图案栅极ARC层和图案化栅极层。 不在图案化栅极层下面的高k栅极电介质层被部分蚀刻，并且形成图案化栅极层的平滑暴露的上表面。 除去不在图案化栅极层下方的部分蚀刻的高k栅极电介质层部分以形成由图案化栅极层和蚀刻的高k栅极电介质层组成的栅电极。

公开(公告)号：US06235653B1

公开(公告)日：2001-05-22

申请号：US09324924

申请日：1999-06-04

申请人： Hung-Ju Chien ,  Yuan-Hung Chiu ,  Wen-Kung Cheng ,  Yin-Lang Wang

发明人： Hung-Ju Chien ,  Yuan-Hung Chiu ,  Wen-Kung Cheng ,  Yin-Lang Wang

IPC分类号： H01L2131

CPC分类号： H01L21/76829 ,  H01L21/3145 ,  H01L21/76807

摘要： A new method of forming a plasma-enhanced silicon-rich oxynitride layer having improved uniformity across the wafer in terms of layer thickness, refractivity, and reflectivity by using argon as the inert carrier gas is described. A semiconductor substrate is provided which may include semiconductor device structures. An Argon-based silicon-rich oxynitride etch stop layer is deposited overlying the semiconductor substrate. An oxide layer is deposited overlying the Argon-based silicon-rich oxynitride etch stop layer. An opening is etched through the oxide layer stopping at the Argon-based silicon-rich oxynitride etch stop layer. Thereafter, the Argon-based silicon-rich oxynitride etch stop layer within the opening is removed. The opening is filled with a conducting layer. This Argon-based silicon-rich oxynitride layer has improved uniformity across the wafer in terms of layer thickness, refractivity, and reflectivity as compared with a helium-based silicon-rich oxynitride layer.

摘要翻译： 描述了通过使用氩作为惰性载气，在层厚度，折射率和反射率方面形成了具有改善的晶片均匀性的等离子体增强的富硅氧氮化物层的新方法。 提供一种可包括半导体器件结构的半导体衬底。 沉积在半导体衬底上的基于氩的富硅氧氮化物蚀刻停止层。 覆盖基于氩的富硅氧氮化物蚀刻停止层上的氧化物层。 蚀刻通过在氩基富硅氧氮化物蚀刻停止层处停止的氧化物层的开口。 此后，除去开口内的基于氩的富硅氧氮化物蚀刻停止层。 开口填充有导电层。 与基于氦的富硅氧氮化物层相比，这种基于氩的富硅氧氮化物层在层厚度，折射率和反射率方面具有改善整个晶片的均匀性。

公开(公告)号：US08614132B2

公开(公告)日：2013-12-24

申请号：US13240025

申请日：2011-09-22

申请人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

发明人： Ming-Huan Tsai ,  Chun-Fai Cheng ,  Hui Ouyang ,  Yuan-Hung Chiu ,  Yen-Ming Chen

IPC分类号： H01L21/336

CPC分类号： H01L29/66515 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite the LDD region.

摘要翻译： 公开了一种用于制造集成电路器件的集成电路器件和方法。 所公开的方法提供对集成电路器件的表面接近度和尖端深度的改进的控制。 在一个实施例中，该方法通过在器件的源极和漏极区域中形成掺杂区域和轻掺杂源极和漏极（LDD）区域来实现改进的控制。 掺杂区域注入与LDD区域相反的掺杂剂类型。

公开(公告)号：US07510940B2

公开(公告)日：2009-03-31

申请号：US11707490

申请日：2007-02-16

申请人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

发明人： Chen-Nan Yeh ,  Mong Song Liang ,  Ryan Chia-Jen Chen ,  Yuan-Hung Chiu

IPC分类号： H01L21/336

CPC分类号： H01L21/823857 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L29/66636 ,  H01L29/7848

摘要： A method for fabricating a dual-gate semiconductor device. A preferred embodiment comprises forming a gate stack having a first portion and a second portion, the first portion and the second portion including a different composition of layers, forming photoresist structures on the gate stack to protect the material to be used for the gate structures, etching away a portion of the unprotected material, forming recesses adjacent to at least one of the gate structures in the substrate upon which the gate structures are disposed, and forming a source region and the drained region in the respective recesses. The remaining portions of the gate stack layers that are not a part of a gate structure are then removed. In a particularly preferred embodiment, an oxide is formed on the vertical sides of the gate structures prior to etching to create the source and drain regions.

摘要翻译： 一种制造双栅极半导体器件的方法。 优选实施例包括形成具有第一部分和第二部分的栅极堆叠，第一部分和第二部分包括不同的层组成，在栅极堆叠上形成光刻胶结构以保护用于栅极结构的材料， 蚀刻掉未被保护材料的一部分，形成与栅极结构设置在其中的基板中的栅极结构中的至少一个相邻的凹槽，以及在各个凹部中形成源极区域和排出区域。 然后去除不是栅极结构的一部分的栅极堆叠层的剩余部分。 在特别优选的实施例中，在蚀刻之前，在栅极结构的垂直侧上形成氧化物以形成源区和漏区。