公开(公告)号：US20240419549A1

公开(公告)日：2024-12-19

申请号：US18821203

申请日：2024-08-30

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: G06F11/10

Abstract: Methods, systems, and devices for parity-based error management are described. A processing system that performs a computational operation on a set of operands may perform a computational operation, (e.g., the same computational operation) on parity bits for the operands. The processing system may then use the parity bits that result from the computational operation on the parity bits to detect, and discretionarily correct, one or more errors in the output that results from the computational operation on the operands.

公开(公告)号：US12073110B2

公开(公告)日：2024-08-27

申请号：US17931262

申请日：2022-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G06F12/00 ,  C12Q1/6869 ,  G06F3/06

CPC classification number: G06F3/0655 ,  C12Q1/6869 ,  G06F3/0604 ,  G06F3/0673

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US12045503B2

公开(公告)日：2024-07-23

申请号：US17515229

申请日：2021-10-29

Applicant: Micron Technology, Inc.

Inventor： Kenneth Marion Curewitz ,  Shivam Swami ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel ,  Sean S. Eilert

IPC: G06F3/06 ,  G06F12/02 ,  H10B63/00

CPC classification number: G06F3/0659 ,  G06F3/0679 ,  G06F12/0246 ,  H10B63/84 ,  G06F3/0622

Abstract: A memory chip having a predefined memory region configured to store program data transmitted from a microchip. The memory chip also having a programmable engine configured to facilitate access to a second memory chip to read data from the second memory chip and write data to the second memory chip according to stored program data in the predefined memory region. The predefined memory region can include a portion configured as a command queue for the programmable engine, and the programmable engine can be configured to facilitate access to the second memory chip according to the command queue.

公开(公告)号：US20240237363A1

公开(公告)日：2024-07-11

申请号：US18400994

申请日：2023-12-29

Applicant: Micron Technology, Inc.

Inventor： James Brian Johnson ,  Brent Keeth ,  Ameen D. Akel ,  Kunal R. Parekh ,  Amy Rae Griffin ,  Eiichi Nakano

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Methods, systems, and devices for modular die configurations for multi-channel memory are described. A semiconductor component (e.g., a semiconductor wafer) may be configured with multiple rows and multiple columns of memory arrays, and associated channels. A row of memory arrays may be associated with a contact region extending along the row direction. The semiconductor component may also include control regions extending along the column direction between at least some of the columns of memory arrays. Each control region may include control circuitry for operating memory arrays on one or both sides of the control region. The channels and memory arrays of the semiconductor wafer may be grouped into one or more independently-operable memory dies, with each memory die having at least a portion of a control region and at least a portion of a contact region for operating the memory arrays of the memory die.

公开(公告)号：US12008460B2

公开(公告)日：2024-06-11

申请号：US17007588

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Dmitri Yudanov ,  Sean S. Eilert ,  Hernan A. Castro ,  Ameen D. Akel

IPC: G06N3/06 ,  G06N3/049 ,  G06N3/063 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

CPC classification number: G06N3/063 ,  G06N3/049 ,  G11C11/4063 ,  G11C11/54 ,  G06N3/084 ,  G06N5/046

Abstract: Spiking events in a spiking neural network may be processed via a memory system. A memory system may store data corresponding to a group of destination neurons. The memory system may, at each time interval of a SNN, pass through data corresponding to a group of pre-synaptic spike events from respective source neurons. The data corresponding to the group of pre-synaptic spike events may be subsequently stored in the memory system.

公开(公告)号：US20240087643A1

公开(公告)日：2024-03-14

申请号：US17931277

申请日：2022-09-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Justin Eno ,  Sean S. Eilert ,  Ameen D. Akel ,  Kenneth M. Curewitz

IPC: G11C13/00 ,  C12Q1/6869 ,  G11C7/16 ,  G16B30/10

CPC classification number: G11C13/0069 ,  C12Q1/6869 ,  G11C7/16 ,  G11C13/004 ,  G16B30/10

Abstract: A memory device may be used to implement a Bloom filter. In some examples, the memory device may include a memory array to perform a multiply-accumulate operation to implement the Bloom filter. The memory device may store multiple portions of a reference genetic sequence in the memory array and compare the portions of the reference genetic sequence to a read sequence in parallel by performing the multiply-accumulate operation. The results of the multiply-accumulate operation between the read sequence and the portions of the reference genetic sequence may be used to determine where the read sequence aligns to the reference sequence.

公开(公告)号：US20240036762A1

公开(公告)日：2024-02-01

申请号：US18227216

申请日：2023-07-27

Applicant: Micron Technology, Inc.

Inventor： Edmund J. Gieske ,  Cagdas Dirik ,  Elliott C. Cooper-Balis ,  Robert M. Walker ,  Amitava Majumdar ,  Sujeet Ayyapureddi ,  Yang Lu ,  Ameen D. Akel ,  Niccolò Izzo ,  Danilo Caraccio ,  Markus H. Geiger

IPC: G06F3/06 ,  G06F12/0802

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0802 ,  G06F2212/60

Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.

公开(公告)号：US20230208444A1

公开(公告)日：2023-06-29

申请号：US17677593

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Ameen D. Akel ,  Helena Caminal ,  Sean S. Eilert

IPC: H03M13/15 ,  H03M13/43 ,  G11C15/04 ,  G06F11/10

CPC classification number: H03M13/1575 ,  G06F11/1068 ,  G11C15/04 ,  H03M13/43

Abstract: Methods, systems, and devices for associative computing for error correction are described. A device may receive first data representative of a first codeword of a size for error correction. The device may identify a set of content-addressable memory cells that stores data representative of a set of codewords each of which is the size of the first codeword. The device may identify second data representative of the first codeword in the set of content-addressable memory cells. Based on identifying the second data, the device may transmit an indication of a valid codeword that is mapped to the second data.

公开(公告)号：US11687282B2

公开(公告)日：2023-06-27

申请号：US17236981

申请日：2021-04-21

Applicant: Micron Technology, Inc.

Inventor： Shivasankar Gunasekaran ,  Samuel E. Bradshaw ,  Justin M. Eno ,  Ameen D. Akel

IPC: G06F3/06 ,  G06F12/0873 ,  G06F11/07

CPC classification number: G06F3/0659 ,  G06F3/0614 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/0757 ,  G06F12/0873

Abstract: A memory sub-system configured to be responsive to a time to live requirement for load commands from a processor. For example, a load command issued by the processor (e.g., SoC) can include, or be associated with, an optional time to live parameter. The parameter requires that the data at the memory address be available within the time specified by the time to live parameter. When the requested data is currently in the lower speed memory (e.g., NAND flash) and not available in the higher speed memory (e.g., DRAM, NVRAM), the memory sub-system can determine that the data cannot be made available with the specified time and optionally skip the operations and return an error response immediately.

公开(公告)号：US11636334B2

公开(公告)日：2023-04-25

申请号：US16545837

申请日：2019-08-20

Applicant: Micron Technology, Inc.

Inventor： Samuel E. Bradshaw ,  Shivasankar Gunasekaran ,  Sean Stephen Eilert ,  Ameen D. Akel ,  Kenneth Marion Curewitz

IPC: G06N3/08 ,  G06F21/60 ,  G06N3/04 ,  G06N20/00 ,  G06F21/62

Abstract: A system having multiple devices that can host different versions of an artificial neural network (ANN). In the system, inputs for the ANN can be obfuscated for centralized training of a master version of the ANN at a first computing device. A second computing device in the system includes memory that stores a local version of the ANN and user data for inputting into the local version. The second computing device includes a processor that extracts features from the user data and obfuscates the extracted features to generate obfuscated user data. The second device includes a transceiver that transmits the obfuscated user data. The first computing device includes a memory that stores the master version of the ANN, a transceiver that receives obfuscated user data transmitted from the second computing device, and a processor that trains the master version based on the received obfuscated user data using machine learning.