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    CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE
    33.
    发明申请
    CONDITIONAL OPERATION IN AN INTERNAL PROCESSOR OF A MEMORY DEVICE 审中-公开

    公开(公告)号：US20170168817A1

    公开(公告)日：2017-06-15

    申请号：US15395602

    申请日：2016-12-30

    Applicant: Micron Technology, Inc.

    Inventor： Robert Walker

    IPC: G06F9/30 ,  G06F9/38

    CPC classification number: G06F15/7821 ,  G06F9/3001 ,  G06F9/30072 ,  G06F9/3877 ,  G06F9/3885 ,  Y02D10/12 ,  Y02D10/13

    Abstract: The present techniques provide an internal processor of a memory device configured to selectively execute instructions in parallel, for example. One such internal processor includes a plurality of arithmetic logic units (ALUs), each connected to conditional masking logic, and each configured to process conditional instructions. A condition instruction may be received by a sequencer of the memory device. Once the condition instruction is received, the sequencer may enable the conditional masking logic of the ALUs. The sequencer may toggle a signal to the conditional masking logic such that the masking logic masks certain instructions if a condition of the condition instruction has been met, and masks other instructions if the condition has not been met. In one embodiment, each ALU in the internal processor may selectively perform instructions in parallel.

    SYSTEMS AND METHODS FOR ACCESSING MEMORY
    35.
    发明申请
    SYSTEMS AND METHODS FOR ACCESSING MEMORY 审中-公开
    用于访问存储器的系统和方法

    公开(公告)号：US20160062909A1

    公开(公告)日：2016-03-03

    申请号：US14936209

    申请日：2015-11-09

    Applicant: Micron Technology, Inc.

    Inventor： Robert Walker

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F9/5016 ,  G06F12/1027 ,  G06F12/109 ,  G06F13/1684 ,  G06F2212/65 ,  G06F2212/657 ,  Y02D10/14 ,  Y02D10/22

    Abstract: Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described.

    Abstract translation: 描述了将存储器单元映射到应用的方法，访问存储器单元，系统和存储器控制器的方法。 在一些实施例中，包括多个物理信道的存储器系统被映射到区域中，使得任何区域跨越存储器系统的每个物理信道。 应用程序在区域中分配内存，并且应用程序的性能和功耗要求与区域相关联。 还描述了附加的方法和系统。

    CONTROL OF PAGE ACCESS IN MEMORY
    36.
    发明申请
    CONTROL OF PAGE ACCESS IN MEMORY 有权
    页面存取控制

    公开(公告)号：US20140258649A1

    公开(公告)日：2014-09-11

    申请号：US14286104

    申请日：2014-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Robert Walker

    IPC: G06F13/16

    CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/00 ,  G06F12/0215 ,  G06F12/06 ,  G06F12/14 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/161 ,  G06F13/1615 ,  G06F13/1668 ,  G06F13/4243 ,  G06F15/7821 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

    Abstract translation: 本技术提供了控制对存储器组件（诸如存储体）中的多个打开页面的访问的系统和方法。 几个组件可以请求访问存储体。 控制器可以接收请求，并根据请求打开或关闭存储体中的页面。 在一些实施例中，控制器分配一些请求访问的组件的优先级，并将存储体中的特定页面分配给优先级组件。 此外，同一内存库中的其他可用页面也可能被其他优先级组件或具有较低优先级的组件打开。 控制器可以节省功率，或者可以通过在超时之后，事务完成之后或响应于主机接收的多个请求来关闭页面，从而提高组件与存储体之间的处理交易的效率。

    SYSTEMS AND METHODS FOR ACCESSING MEMORY
    37.
    发明申请
    SYSTEMS AND METHODS FOR ACCESSING MEMORY 有权
    用于访问存储器的系统和方法

    公开(公告)号：US20140208060A1

    公开(公告)日：2014-07-24

    申请号：US13746141

    申请日：2013-01-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Robert Walker

    IPC: G06F12/10

    CPC classification number: G06F12/1009 ,  G06F9/5016 ,  G06F12/1027 ,  G06F12/109 ,  G06F13/1684 ,  G06F2212/65 ,  G06F2212/657 ,  Y02D10/14 ,  Y02D10/22

    Abstract: Methods of mapping memory cells to applications, methods of accessing memory cells, systems, and memory controllers are described. In some embodiments, a memory system including multiple physical channels is mapped into regions, such that any region spans each physical channel of the memory system. Applications are allocated memory in the regions, and performance and power requirements of the applications are associated with the regions. Additional methods and systems are also described.

    Abstract translation: 描述了将存储器单元映射到应用的方法，访问存储器单元，系统和存储器控制器的方法。 在一些实施例中，包括多个物理信道的存储器系统被映射到区域中，使得任何区域跨越存储器系统的每个物理信道。 应用程序在区域中分配内存，并且应用程序的性能和功耗要求与区域相关联。 还描述了附加的方法和系统。

    CONTROL OF PAGE ACCESS IN MEMORY
    38.
    发明申请
    CONTROL OF PAGE ACCESS IN MEMORY 有权
    页面存取控制

    公开(公告)号：US20130145114A1

    公开(公告)日：2013-06-06

    申请号：US13750560

    申请日：2013-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Robert Walker

    IPC: G06F12/14

    CPC classification number: G06F3/0622 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0644 ,  G06F3/0688 ,  G06F3/0689 ,  G06F12/00 ,  G06F12/0215 ,  G06F12/06 ,  G06F12/14 ,  G06F13/00 ,  G06F13/14 ,  G06F13/16 ,  G06F13/161 ,  G06F13/1615 ,  G06F13/1668 ,  G06F13/4243 ,  G06F15/7821 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

    Abstract: The present techniques provide systems and methods of controlling access to more than one open page in a memory component, such as a memory bank. Several components may request access to the memory banks. A controller can receive the requests and open or close the pages in the memory bank in response to the requests. In some embodiments, the controller assigns priority to some components requesting access, and assigns a specific page in a memory bank to the priority component. Further, additional available pages in the same memory bank may also be opened by other priority components, or by components with lower priorities. The controller may conserve power, or may increase the efficiency of processing transactions between components and the memory bank by closing pages after time outs, after transactions are complete, or in response to a number of requests received by masters.

    Abstract translation: 本技术提供了控制对存储器组件（诸如存储体）中的多个打开页面的访问的系统和方法。 几个组件可以请求访问存储体。 控制器可以接收请求，并根据请求打开或关闭存储体中的页面。 在一些实施例中，控制器分配一些请求访问的组件的优先级，并将存储体中的特定页面分配给优先级组件。 此外，同一内存库中的其他可用页面也可能被其他优先级组件或具有较低优先级的组件打开。 控制器可以节省功率，或者可以通过在超时之后，事务完成之后或响应于主机接收的多个请求来关闭页面，从而提高组件与存储体之间的处理交易的效率。

    MEMORY CONTROLLER WITH TIME-BASED READ AND WRITE PHASES
    39.
    发明公开
    MEMORY CONTROLLER WITH TIME-BASED READ AND WRITE PHASES 审中-公开

    公开(公告)号：US20240281141A1

    公开(公告)日：2024-08-22

    申请号：US18443956

    申请日：2024-02-16

    Applicant: Micron Technology, Inc.

    Inventor： Patrick A. La Fratta ,  Robert Walker

    IPC: G06F3/06

    CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

    Abstract: Better command scheduling in a memory controller can help improve memory device bandwidth utilization. A method for command scheduling in a memory controller can include processing commands of exclusively a first command type from a command queue including transmitting data in a first direction using a data bus for a first duration. Responsive to determining the first duration meets or exceeds a specified time or cycle limit, the bus can be turned around to accommodate transactions or commands of a second type. Following the bus turnaround, the method can include processing commands of exclusively a second command type from the command queue including transmitting data in a second direction using the data bus. The time or cycle limit can be statically or dynamically adjusted, for example, based on a read/write mix of commands in the command queue.

    Response-based interconnect control
    40.
    发明授权
    Response-based interconnect control 有权

    公开(公告)号：US11734203B2

    公开(公告)日：2023-08-22

    申请号：US17556908

    申请日：2021-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Robert Walker ,  Nikesh Agarwal

    IPC: G06F13/16 ,  H04L47/10 ,  G06F9/30

    CPC classification number: G06F13/1621 ,  G06F9/30043 ,  G06F9/30101 ,  G06F13/1642 ,  G06F13/1668 ,  H04L47/39

    Abstract: Described apparatuses and methods enable a receiver of requests, such as a memory device, to control the arrival of future requests using a credit-based communication protocol. A transmitter of requests can be authorized to transmit a request across an interconnect responsive to possession of a credit. If the transmitter exhausts its credits, the transmitter waits until a credit is returned before transmitting another request. The receiver can manage credit returns based on how many responses are present in a response queue. The receiver can change a rate at which the credit returns are transmitted by changing a size of an interval of responses that are being transmitted, with one credit being returned per interval. This can slow the rate of credit returns while the response queue is relatively more filled. The rate adjustment can decrease latency by reducing an amount of requests or responses that are pooling in backend components.

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